MPC8280 Motorola, MPC8280 Datasheet - Page 41

• Manufacturer Part Number: MPC8280
• Description: PowerQUICC II Family Hardware Specifications
• Manufacturer: Motorola

1
2
3
4
5
8
This section provides the pin assignments and pinout lists for both HiP7 PowerQUICC II packages.
8.1
The following figures and table represent the standard 480 TBGA package. For information on the alternate
package, refer to Section 8.2, “VR and ZQ Packages—MPC8275 and MPC8270” on page 56.
Figure 13 shows the pinout of the ZU package as viewed from the top surface.
MOTOROLA
As shown in Table 14, PCI_MODCK determines the PCI clock range. Refer to Table 18 for higher range configurations.
MODCK_H = hard reset configuration word [28–31]. MODCK[1-3] = three hardware configuration pins.
CPM multiplication factor = CPM clock/PCI clock
CPU multiplication factor = Core PLL multiplication factor
the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock mode.
For modes with a CPU multiplication factor ≤ 3, the minimum CPU frequency is 166 MHz. The minimum CPM frequency
is 133 MHz.
For modes with a CPU multiplication factor ≥ 3.5, the minimum CPU frequency is 250 MHz. The minimum CPM
frequency is as shown in the table.
“High” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the
resulting configuration does not exceed the frequency rating of the user’s device.
“Low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency guarantees
Pinout
ZU Package—MPC8280 and MPC8270
MPC8280 PowerQUICC II™ Family Hardware Specifications
Pinout
41