MPC8280 Motorola, MPC8280 Datasheet - Page 24

• Manufacturer Part Number: MPC8280
• Description: PowerQUICC II Family Hardware Specifications
• Manufacturer: Motorola

In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven
bits during the power-up reset—three hardware configuration pins (MODCK[1–3]) and four bits from
hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the
selected MPC8280 clock operation mode as described in the following sections.
7.1
Table 15 lists clock configurations for the MPC8280 in local bus mode. The frequencies listed are for the
purpose of illustration only. Users must select a mode and input bus frequency so that the resulting
configuration does not exceed the frequency rating of the user’s device.
MODCK_H-MODCK[1-3]
24
0000_000
0000_001
0000_010
0000_011
0000_100
0000_101
0000_110
0000_111
0001_000
0001_001
0001_010
0001_011
0001_100
0001_101
0001_110
1000_111
0001_111
0010_000
0010_001
Mode
Local Bus Mode
2
Clock configurations change only after PORESET is asserted.
MPC8280 PowerQUICC II™ Family Hardware Specifications
Table 15. Clock Configurations for Local Bus Mode
62.5
50.0
62.5
50.0
66.7
66.7
66.7
55.5
66.7
66.7
66.7
62.5
50.0
45.5
44.3
low
Bus Clock
(MHz)
133.3
133.3
100.0
100.0
167.0
167.0
160.0
160.0
167.0
167.0
167.0
133.3
133.3
133.3
133.3
high
3
Default Modes (MODCK_H= 0000)
Multiplication
Full Configuration Modes
Factor
CPM
2.5
2.5
3
3
4
4
2
2
2
2
2
3
3
3
3
NOTE
4
187.5
150.0
250.0
200.0
133.3
133.3
166.7
138.7
133.3
133.3
133.3
187.5
150.0
136.4
133.3
low
CPM Clock
Reserved
Reserved
Reserved
Reserved
(MHz)
400.0
400.0
400.0
400.0
334.0
334.0
400.0
400.0
334.0
334.0
334.0
400.0
400.0
400.0
400.0
high
Multiplication
Factor
CPU
2.5
2.5
5.5
1
4
5
4
5
3
3
4
5
6
4
5
6
5
250.0
250.0
250.0
250.0
166.7
200.0
166.7
166.7
266.7
333.3
396.0
250.0
250.0
250.0
266.7
low
CPU Clock
MOTOROLA
(MHz)
1002.0
533.3
666.7
400.0
500.0
417.5
501.0
400.0
480.0
668.0
835.0
533.3
666.7
733.3
800.0
high