MTC20454 ST Microelectronics, Inc., MTC20454 Datasheet - Page 12

• Manufacturer Part Number: MTC20454
• Description: Quad Integrated Adsl CMOS Analog Front End Circuit
• Manufacturer: ST Microelectronics, Inc.

MTC20454
Receive / Transmit Interface Timing
This interface is a triple (RX,TX, TXE) nibble-serial interface running at 8.8 MHz sampling (normal mode).
The data are represented in 16 bits format, and transferred in groups of 4 bits (nibbles). The LSBs are
transferred first. The MTC20454 generates a nibble clock (= master clock in normal mode, CLKNIB in
OSR = 2 mode) and word signals shared by the three interfaces.
Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the low going
edge of CLKM/CLKNIB. This holds for the data stream from MTC20454 and rom the digital processor. Da-
ta,
CLWD set-up and hold times are 5 ns with reference to the falling edge of CLKM/CLKNIB. RXD is sampled
with CLKM rising edge.
Figure 8. TX/RX Digital Interface Timing
Table 5. TX/RX Digital Interface timing
Reset Function
The MTC20454 is placed in reset mode when the RESETN pin is pulled to ground (active low signal). The
chip status is depicted in the following table:
12/15
CLKM pin is replicating the CLKIN input clock. System clock available
CLKWD is not generated. The pin stays at high level
Digital blocks are in reset: no activity
Analog blocks are in powerdown
External driver is forced to powerdown
Symbol
Tdv
Ts
Th
35.328Mhz
8.832Mhz
CLKWD
CLKM
RXDx
TXDx
Parameter
Setup time
Data valid
Hold time
N0
Ts
N1
Tdv
Tdv
Th
N2
Reset
N3
0.5 ns
0.2 ns
0.5 ns
Min
Typ
-
-
-
Max
4 ns
-
-