MTC20454 ST Microelectronics, Inc., MTC20454 Datasheet - Page 11

• Manufacturer Part Number: MTC20454
• Description: Quad Integrated Adsl CMOS Analog Front End Circuit
• Manufacturer: ST Microelectronics, Inc.

Receive / Transmit Interface
The digital interface is based on a 4 * 8.832 MHz (35.328 MHz) clock. The 8.832MHz 12 bits A/D output
signal or the D/A input signal are SIPO multiplexed over 4 parallel 35.328MHz data lines in the following
table. If OSR = 2 bit is selected, CLKNIB is used as nibble clock (17.664 MHz, disabled in normal mode),
and all the
Table 2. RXi, TXi, CLKWD periods are twice
TX / TXE Signal Dynamic Range
The dynamic range of the signal for both DACs is 12 bits extracted from the available signed 16 bit repre-
sentation coming from the digital processor.
The maximal positive number is 2 11 -1, the most negative number is -2 11, the 3 least significant bits are
ignored.
Any signal exceeding these limits is clamped to the maximal value.
Table 3. TX bit map
RX Signal Dynamic Range
The dynamic range of the signal from the ADC is limited to 13 bits. hose bits are converted to a signed
representation with a maximal positive number of 2 12 -1 and a most negative number of -2 12.
The 2 LSBs are filled with ‘0’.
Table 4. RX bit map in normal mode
Sign
Sign
Sign
B12
Packet Number
B10
B11
Packet 1
Packet 2
Packet 3
Packet 4
B10
B9
B8
B9
B7
B8
B6
B7
B5
B6
Bus Line
RX0/TX0
RX1/TX1
RX2/TX2
RX3/TX3
RX0/TX0
RX1/TX1
RX2/TX2
RX3/TX3
RX0/TX0
RX1/TX1
RX2/TX2
RX3/TX3
RX0/TX0
RX1/TX1
RX2/TX2
RX3/TX3
B4
B5
B3
B4
B2
B3
B1
B2
B0
B1
Word bit
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
n.u
B0
MTC20454
n.u
0
11/15
n.u
0