MTC20154-TQ-C2 ST Microelectronics, Inc., MTC20154-TQ-C2 Datasheet - Page 17

• Manufacturer Part Number: MTC20154-TQ-C2
• Description: Integrated Adsl CMOS Analog Front-end Circuit
• Manufacturer: ST Microelectronics, Inc.

Table 21. Receive / Transmit Protocol
Data set up and hold time are specified versus rising edge of CLKM
Receive / Transmit Interface
The digital interface is based on a 4 * 8.832 MHz (35.328 MHz) clock. The 8.832MHz 12 bits A/D output
signal or the D/A input signal are SIPO multiplexed over 4 parallel 35.328 MHz data lines in the following
table.
If OSR = 2 bit is selected, CLKNIB is used as nibble clock (17.664 MHz, disabled in normal mode), and
all the RXi, TXi, CLKWD periods are twice as long as in normal mode.
Table 22. Receive / Transmit Protocol
TX / TXE Signal Dynamic Range
The dynamic range of the signal for both DACs is 12 bits extracted from the available signed 16 bit repre-
sentation coming from the digital processor. The maximal positive number is 2
number is -2
Figure 10. TX/TXE Bit Map
RX Signal Dynamic Range
The dynamic range of the signal from the ADC is limited to 13 bits. Those bits are converted to a signed
representation with a maximal positive number of 2
are filled with ’0’.
Figure 11. RX Bit Map
RXD0 / TXD0 will contain
RXD1 / TXD1 will contain
RXD2 / TXD2 will contain
RXD3 / TXD3 will contain
sign
sign
Symbol
TDv
Ts
Th
sign
b12
14
, the 3 LSBs are ignored. Any signal exceeding these limits is clamped to the maximal value.
b10
b11
b10
b9
Parameters
Setup Time
Data Valid
Hold time
b9
b8
b7
b8
b6
b7
0.2 ns
0.5 ns
7 ns
min
b6
b5
14
-1 and a most negative number of 2
b4
b5
N0
b0
b1
b2
b3
b3
b4
typ
–
–
–
b3
b2
N1
b4
b5
b6
b7
b2
b1
max
4 ns
–
–
b0
b1
14
-1, the most negative
b10
b11
N2
b8
b9
n.u.
b0
14
Remarks
. The 2 LSBs
MTC20154
n.u.
0
b12
b13
b14
b15
N3
n.u.
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0