MTC20154-TQ-C2 ST Microelectronics, Inc., MTC20154-TQ-C2 Datasheet - Page 16

• Manufacturer Part Number: MTC20154-TQ-C2
• Description: Integrated Adsl CMOS Analog Front-end Circuit
• Manufacturer: ST Microelectronics, Inc.

MTC20154
The crystal’s exact oscillation frequency can be tuned around the nominal frequency. This is needed in
order to allow the system to minimize the clock phase shift between the LT and the NT modems. The in-
formation coming from the digital processor via the CTRLIN path is used to drive a 8 bits DAC (resistor
ladder architecture) which generates a control current. This current is externally converted and filtered to
generate the required control voltage for the varicap. The VCXO characteristics are given in the following
table.
Table 20. VCXO characteristics
PLL Based Frequency Doubler
Dual crystal frequency can now be used needed when a 17.644 MHz crystal with the MTC20154 on–board
crystal
Loop (PLL), frequency of 35.328 MHz is still
Digital Interface
Control Interface
The digital code setting for the MTC20154 configuration is sent over a serial line (CTRLIN) using the word
clock (CLWD). The data burst is composed of 16 bits from which the first bit is used as start bit (’0’), the
three LSBs being used to identify the data contained in the 12 remaining bits. Test related data are latched
but they are overruled by the normal settings if the TEST pin is low.
Control Interface Timing
The control interface bits are considered valid on each positive edge of the master clock (CLKM). They
will be sampled at this moment. The stop bit will trigger the internal data validation. The timing require-
ments are depicted in the following figure and table:
Figure 9. Control Interface Timing diagram
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Needed crystal accuracy
Needed crystal frequency tuning range
DAC resolution
DAC output voltage range
DAC differential non linearity error
DAC integrated non linearity error
VCXO nominal output current
(Rref = 16.5 K AVDD = 3.3 V)
Power consumption
is used. A frequency doubler, build driver. However, a master clock
CLKWD
CTRLIN
CLKM
Data
Start
bit
Ts
Th
ctrl data bits
Min
100
will then be used.
50
95
–
–
–
–
-
AVDD/2
Typical
.225
100
ctrl cmd bits 1 stop bit (high)
–
–
8
–
–
up around a Phase Locked
Max
105
1.5
–
–
–
4
–
-
Unity
ppm
ppm
LSB
LSB
mW
mA
bit
V