MT93L04 Zarlink Semiconductor, MT93L04 Datasheet - Page 17

• Manufacturer Part Number: MT93L04
• Description: 128-channel Voice Echo Canceller
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
PLLVSS2_d3
AT1_d3
DEVICE 4
TMS_d4
TDI_d4
TDO_d4
TCK_d4
TRSTB_d4
Test_En_d4
RESETB_d4
IRQB_d4
DSB_d4
Signal Name
Power
NC
Signal
Signal
Signal
Signal
Signal
ICO
Signal
Signal
Signal
Signal Type
V12
U12
E16
D17
C18
F16
E17
G16
F17
G17
H16
BGA Ball #
Zarlink Semiconductor Inc.
MT93L04
17
PLL Ground. Must be connected to VSS
No connection. The pin must be left open for
normal operation.
Test Mode Select (3.3 V Input). JTAG signal that
controls the state transitions of the TAP controller.
This pin is pulled high by an internal pull-up when
not driven.
Test Serial Data In (3.3 V Input). JTAG serial test
instructions and data are shifted in on this pin.
This pin is pulled high by an internal pull-up when
not driven.
Test Serial Data Out (Output). JTAG serial data
is output on this pin on the falling edge of TCK.
This pin is held in high impedance state when
JTAG scan is not enabled.
Test Clock (3.3 V Input). Provides the clock to
the JTAG test logic.
Test Reset (3.3 V Input). Asynchronously
initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be
pulsed low on power-up or held low, to ensure that
the MT93L00 is in the normal functional mode.
This pin is pulled by an internal pull-down when
not driven.
Internal Connection. Connected to VSS for
normal operation
Device Reset (Schmitt Trigger Input). An active
low resets the device and puts the MT93L00 into a
low-power stand-by mode.
When the RESET pin is returned to logic high
and a clock is applied to the MCLK pin, the
device will automatically execute initialization
routines, which preset all the Control and Status
Registers to their default power-up values.
Interrupt Request (Open Drain Output). This
output goes low when an interrupt occurs in any
channel. IRQ returns high when all the interrupts
have been read from the Interrupt FIFO Register.
A pull-up resistor (1 K typical) is required at this
output.
Data Strobe (Input). This active low input works
in conjunction with CS to enable the read and
write operations.
Signal Description
Data Sheet