MT92220 Zarlink Semiconductor, MT92220 Datasheet - Page 25

• Manufacturer Part Number: MT92220
• Description: 1023 Channel Voice Over IP/AAL2 Processor
• Manufacturer: Zarlink Semiconductor

Data Sheet
3.0
The objective of the MT92220 device is to transport voice information encapsulated in IP packets over network
connections. Therefore, to allow maximum flexibility, it can support 3 different types of link interfaces: Ethernet,
UTOPIA and Packet over SONET.
The network module of the chip is responsible for the identification and routing of packets, deciding which packets
should be kept and treated as voice, which should be routed to the data packet buffer and which should be
discarded. Furthermore, on its UTOPIA interfaces, the MT92220 can also receive AAL2 cells and route them to an
AAL2 treatment block.
The network module accepts packets that are generated by the Packet Assembly module, as well as packets
received from either of the two RX link ports. In the TX direction, it can send packets to the Packet Disassembly
module, as well as to any of 4 TX link buffers: TX link A High-Priority, TX link A Low-Priority, TX link B High-Priority
and TX link B Low-Priority.
It can also receive cells from its twin UTOPIA ports, the TX AAL2 agent or from the TX CPU cell queue and can
route them to the RX AAL2 cell buffer, the RX CPU cell buffer, or one of 4 TX link A cell queues (in priority) or one
of 2 cell queues going to TX link B.
The following figure gives an overview of the data path in the network module, including all the queues that are
used to buffer the data along the way:
:
Disassembly
S Traffic Smoothing Processes (single leaky bucket)
mem_clk_sar_i
Clock Net
Assembly
Module
Module
Network Interface Buffering
Bufferless Process
Buffer in Internal Memory
Payload and Descriptor in SSRAM C
Payload in SDRAM C, Descriptor in SSRAM C
Clock domain crossings
Network Interface
Disassembly
Data FIFO
Data FIFO
Assembly
512 x 32
512 x 32
Packet
Packet
mem_clk_net_i
Clock Net
RXCPU
Agent
AAL2
RX
RXCPU
Agent
Disassembly
TXCPU
Agent
Copying
Assembly
AAL2
Process
Copying
Process
TX
Cell Buffer
RX AAL2
Raw Cell
RX CPU
Packet Buffer
Buffer
Network CPU
Disassembly
Buffer
Figure 3 - Network Interface Buffering
Identifier
Packet
HP Packet
LP Packet
HP Packet
LP Packet
TX Link B
TX Link B
TX Link B
TX Link B
TX Link A
TX Link A
TX Link A
TX Link A
TX Link A
TX Link A
Raw Cell
Raw Cell
Raw Cell
Raw Cell
Raw Cell
Raw Cell
Buffer 0
Buffer 1
Buffer 0
Buffer 1
Buffer 2
Buffer 3
Buffer
Buffer
Buffer
Buffer
Identification
Packet
Buffer
Zarlink Semiconductor Inc.
LP
HP
HP
TX Link
TX Link
LP
B Copy
A Copy
S
Reassembly
Reassembly
Packet
Packet
Buffer
Cell FIFO
TX Link A
128 x 32
Note: Only one type for port A is supported at once (UTOPIA, Ethernet or POS-PHY)
S
RX Link A
Cell FIFO
128 x 32
RX Link B
Cell FIFO
128 x 32
Cells to
Packet
AAL5
to AAL5
Packet
Look-up
Engine
Cells
Based
ATM
Packet/Cell
TX Link A
128 x 36
FIFO
RX Packet FIFO
Ethernet/POS
UTOPIA RX B
UTOPIA RX A
128 x 36
TX Link B
Cell FIFO
128 x 32
Input FIFO
Input FIFO
128 x 16
128 x 16
txa_clk or etha_tx_clk Clock Net
rxa_clk or etha_rx_clk Clock Net
rxb_clk Clock Net
txb_clk Clock Net
UTOPIA
UTOPIA
UTOPIA
UTOPIA
Ethernet
TX POS-
RX POS-
Ethernet
RX
RX
TX
TX
PHY
PHY
TX
RX
TXB
UTOPIA
TXA
UTOPIA
TXA MII
TXA
POS-PHY
NETOWORK_IF
RXB
UTOPIA
RXA
UTOPIA
RXA
POS-PHY
RXA MII
MT92220
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