MT92220 Zarlink Semiconductor, MT92220 Datasheet - Page 158

• Manufacturer Part Number: MT92220
• Description: 1023 Channel Voice Over IP/AAL2 Processor
• Manufacturer: Zarlink Semiconductor

158
11.1
When operating as a slave, the interface has the choice between clocking on A, clocking on B, clocking on A with B
as backup or clocking on B with A as backup. When set to perform automatic switchover, the interface monitors the
current bus master to see if its ct_c8 and ct_frame signals are still valid. The ct_c8 signal is checked to see if its
clock edges are within ± 35 ns of where they are supposed to be (122 ns apart). The ct_frame signal is checked to
make sure that it occurs exactly once every 1024 ct_c8 clock cycles. If either of these two errors is reported about
a given pair of bus master signals, the pair is considered invalid and the slave will switch to the backup master if
any has been programmed to do so. The MT92220 will always monitor these signals and report errors on either of
the two bus masters, even if it does not act on these errors.
11.2
When acting as a bus master, the MT92220 can choose to be a bus master on A, master on B, backup on A or
backup on B. When acting as a bus backup, the MT92220 uses the same error signals described above to
determine if the current bus master is still valid or if it should take over the bus. Note that the bus mastership can be
overridden in registers by ensuring that the chip cannot drive the H.110 clock and frame signals: this will ensure that
it remains a passive slave on the bus. If the chip is a backup on the bus and the primary master fails, it will stop
synchronizing itself on the master and track the local reference.
The chip can also control all the compatibility clocks that must be generated on H.110. There are a good number of
these signals and their generation is independent of the mastership on either A or B: the chip can choose to
generate all of these, or not, whether or not it is bus master or backup. Because these compatibility signals are, by
definition, used to meet the specific requirements of an older bus standard, their generation is not programmable for
the most part.
fr_comp (8M,Strdl)
fr_comp (4M,Strdl)
fr_comp (2M,Strdl)
fr_comp (8M,Last)
fr_comp (4M,Last)
fr_comp (2M,Last)
fr_comp (8M,First)
fr_comp (4M,First)
fr_comp (2M,First)
Slave Mode
Bus Master Mode
Note: The fr_comp polarity in this drawing is always active low for simplicity. It can also be programmed active high.
ct_frame
ct_c8
Figure 92 - TDM Bus Timing - fr_comp Generation
Zarlink Semiconductor Inc.