MT90401 Zarlink Semiconductor, MT90401 Datasheet - Page 25

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MT90401

Manufacturer Part Number
MT90401
Description
Sonet/sdh System Synchronizer
Manufacturer
Zarlink Semiconductor
Datasheet

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5.5
Two control registers are available to program the output phase offset of the generated clocks. All 16.384 MHz
derived outputs clocks, F16o, F80, F0o, C16o, C8o, C4o and C2o can be collectively shifted up to 125
microseconds with a step size of 60 nS with respect to the input reference by programming the Set Delay Word 1
and Set Delay Word 2 registers.
Control and Status Registers
00H (Table 6)
01H (Table 7)
02H
03H
04H (Table 8)
05H
06H (Table 9)
07H (Table 10)
08H
09H
0AH
0BH
0CH
0DH
(A
6
A
Output Phase Adjustment
5
Address
A
4
A
3
A
2
A
1
A
0
)
Control Register 1
Status Register 1
Reserved
Reserved
Control Register 2
Reserved
Set Delay Word 2
Set Delay Word 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register
Table 5 - Register Map
Zarlink Semiconductor Inc.
MT90401
25
Read/
Read/
Read/
Read/
Read/
Read/
/Write
Write
Write
Read
Read
Read
Write
Read
Write
Write
Write
Read
Read
Read
Read
Read
Only
Only
Only
Only
Only
Only
Only
Only
RSEL, FS2, FS1, MS2, MS1, SONET/SDH
FLOCK, TCLR
PRIOOR,
RSV, FLim, RSV, RSV
E3/DS3/OC3,
RSV=0, RSV=0, RSV=0, RSV=0.
Set all bits to zero.
RSV=0,
C16OCNT10,C16OCNT9, C16OCNT8
C16OCNT7-0
Set all bits to zero.
RSV=0,
SECOOR,
E3/DS3,
Function
RSV=0,
LOCK,
RSV=0,
RSV=0,
HOLDOVER,
Data Sheet
RSV=0,
OffEn,

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