MT90401 Zarlink Semiconductor, MT90401 Datasheet - Page 13

• Manufacturer Part Number: MT90401
• Description: Sonet/sdh System Synchronizer
• Manufacturer: Zarlink Semiconductor

MT90401
Data Sheet
Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical
to the line frequency), and the input phase offset is small enough such that no phase slope limiting is exhibited, then
the lock signal will be set high.
1.5
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure
5. The Output Interface Circuit uses five Tapped Delay Lines in MT90401 followed by a T1 Divider Circuit, an E1
Divider Circuit, a DS2 Divider Circuit, and a x4/x8 PLL, to generate the required output signals.
Five tapped delay lines are used to generate 8.592MHz, 11.184MHz, 16.384MHz, 12.352MHz, 12.624MHz and
19.44 MHz signals.
The E1 Divider Circuit uses the 16.384MHz signal to generate four clock outputs and three frame pulse outputs.
The C8o, C4o and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.
These outputs have a nominal 50% duty cycle. The frame pulse outputs (F0o, F8o, and F16o) are generated
directly from the C16 clock.
The T1 Divider Circuit uses the 12.352MHz signal to generate C1.5o. This output has a nominal 50% duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal
50% duty cycle.
The 19.44MHz signal is output on the C19o pin and it is multiplied by an internal PLL to generate the 155.52MHz
clock output on the C155P/N pins. The C155P/N clock has a nominal 50% duty cycle.
The 8.592MHz and 11.184 MHz signals are multiplied by an internal PLL to generate the 34.368MHz or 44.736MHz
clock output on the C34/C44 pin. If the internal PLL is dedicated to the C155P/N clock then the C34/C44 pin will
output the 8.592MHz or 11.184 MHz clocks. The 34.368Mhz and 44.736MHz clocks have a nominal 50% duty
cycle. The duty cycles of the 8.592MHz and 11.184MHz signals are dependent on the duty cycle of the 20MHz
clock input to the C20i pin.
13
Zarlink Semiconductor Inc.