ICE3BR0665JZ Infineon Technologies, ICE3BR0665JZ Datasheet - Page 29

• Manufacturer Part Number: ICE3BR0665JZ
• Description: Off-Line SMPS Current Mode Controller
• Manufacturer: Infineon Technologies

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9
Figure 35
General guideline for PCB layout design using F3/F3R CoolSET
1. “Star Ground “at bulk capacitor ground, C11:
Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 35):
1. Add spark gap
Version 2.0
2. High voltage traces clearance:
3. Filter capacitor close to the controller ground:
a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:
a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm
b. 600V traces (drain voltage of CoolSET
a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.
b. DC ground of the current sense resistor, R12
c. DC ground of the CoolSET
d. DC ground from bridge rectifier, BR1
e. DC ground from the bridging Y-capacitor, C4
High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.
Spark Gap 1
Spark Gap 2
Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated
Gap separation is around 1.5mm (no safety concern)
charge during surge test through the sharp point of the saw-tooth plate.
Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin
as possible so as to reduce the switching noise coupled into the controller.
separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET
effectively. The primary DC grounds include the followings.
“Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11
of IC12 should be connected to the GND pin of IC11 and then “star “connect to the bulk capacitor ground.
GND
L
N
FUSE1
Schematic for recommended PCB layout
Y-CAP
Schematic for recommended PCB layout
C2
X-CAP
C1
C3
Y-CAP
Spark Gap 4
Spark Gap 3
F3 CoolSET schematic for recommended PCB layout
L1
®
C4
Y-CAP
device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector
BR1
®
C11
IC11) to nearby trace: > 2.5mm
R12
C13
bulk cap
*
BA
GND
D11
CS
C14
IC11
CoolSET
F3
FB
29
Schematic for recommended PCB layout
C15
DRAIN
VCC
NC
®
R11
R13
Z11
(refer to Figure 35):
R14
D11
C16
D13
C12
TR1
IC12
D21
R23
ICE3BR0665JZ
C21
R22
C23
IC21
C22
R25
R21
R24
12 Nov 2009
®
GND
device
Vo