LPC2158 NXP Semiconductors, LPC2158 Datasheet - Page 21

• Manufacturer Part Number: LPC2158
• Description: Single-chip 16-bit/32-bit microcontrollers; 512 kB fash
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2157_2158_2
Product data sheet
6.14.1 Features
6.15.1 Features
6.15 General purpose timers/external event counters
slave can communicate on the bus during a given data transfer. The SSP supports full
duplex transfers, with data frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. Often only one of these data flows carries
meaningful data.
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
The LPC2157/2158 can count external events on one of the capture inputs if the minimum
external pulse is equal or longer than a period of the PCLK. In this configuration, unused
capture lines can be selected as regular timer capture inputs, or used as external
interrupts.
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Compatible with Motorola’s SPI, TI’s 4-wire SSI and National Semiconductor’s
Microwire buses.
Synchronous serial communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
Four bits to 16 bits per frame.
A 32-bit timer/counter with a programmable 32-bit prescaler.
External event counter or timer operation.
Four 32-bit capture channels per timer/counter that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Four external outputs per timer/counter corresponding to match registers, with the
following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
Rev. 02 — 9 February 2009
Single-chip 16-bit/32-bit microcontrollers
LPC2157/2158
© NXP B.V. 2009. All rights reserved.
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