AT91FR40162S ATMEL Corporation, AT91FR40162S Datasheet - Page 11

• Manufacturer Part Number: AT91FR40162S
• Description: MicroControllers
• Manufacturer: ATMEL Corporation

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DataSheet
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Flash Memory
The External Bus Interface features also the Early Read Protocol, configurable for all the
devices, that significantly reduces access time requirements on an external device in the case
of single-clock cycle access.
In the AT91FR40162S, the External Bus Interface connects internally to the Flash memory.
The 2-Mbyte Flash memory is organized as 1, 048, 576 words of 16 bits each. The Flash
memory is addressed as 16-bit words via the EBI. It uses address lines A1 - A20 of the
processor.
The address, data and control signals, except the Flash memory enable, are internally inter-
connected. The user should connect the Flash memory enable (NCSF) to one of the active-
low chip selects on the EBI; NCS0 must be used if the Flash memory is to be the boot mem-
ory. In addition, if the Flash memory is to be used as boot memory, the BMS input must be
pulled down externally in order for the processor to perform correct 16-bit fetches after reset.
During boot, the EBI must be configured with correct number of standard wait states. As an
example, five standard wait states are required when the microcontroller is running at 66 MHz.
The user must ensure that all VDDIO, VDDCORE and all GND pins are connected to their
respective supplies by the shortest route. The Flash memory powers-on in read mode. Com-
mand sequences are used to place the device in other operating modes, such as program and
erase.
A separate Flash memory reset input pin (NRSTF) is provided for maximum flexibility,
enabling the reset operation to adapt to the application. When this input is at a logic high level,
the memory is in its standard operating mode; a low level on this input halts the current mem-
ory operation and puts its outputs in a high impedance state.
The Flash memory features data polling to detect the end of a program cycle. While a program
cycle is in progress, an attempted read of the last word written will return the complement of
the written data on I/O7. An open-drain NBUSY output pin provides another method of detect-
ing the end of a program or erase cycle. This pin is pulled low while program and erase cycles
are in progress and is released at the completion of the cycle. A toggle bit feature provides a
third means of detecting the end of a program or erase cycle.
The Flash memory is divided into 39 sectors for erase operations. To further enhance device
flexibility, an Erase Suspend feature is offered. This feature puts the erase cycle on hold for an
indefinite period and allows the user to read data from, or to write data to, any other sector
within the same memory plane. There is no need to suspend an erase cycle if the data to be
read is in the other memory plane.
The device has the capability to protect data stored in any sector. Once the data protection for
a sector is enabled, the data in that sector cannot be changed while input levels lie between
ground and VDDIO.
Note: This data protection does not prevent read accesses of the FLASH.
An optional VPP pin is available to enhance program/erase times.
A 6-byte command sequence (Enter Single Pulse Program Mode) allows the device to be writ-
ten to directly, using single pulses on the write control lines. This mode (Single-pulse
Programming) is exited by powering down the device or by pulsing the NRSTF pin low for a
defined duration and then bringing it back to VDDIO.
AT91FR40162S
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