AD8310 Analog Devices, AD8310 Datasheet - Page 9

• Manufacturer Part Number: AD8310
• Description: Fast Response, DC - 440 Mhz, Voltage Out, 90 DB Logarithmic Amplifier
• Manufacturer: Analog Devices

Input Interface
Figure 22 shows the essentials of the input interface. C
are parasitic capacitances; C
largely due to Q1 and Q2. In most applications both input pins
are ac-coupled. The switches S close when Enable is asserted.
When disabled, bias current I
thus, the coupling capacitors remain charged. If the log amp is
disabled for long periods, small leakage currents will discharge
these capacitors. Then, if they are poorly matched, charging
currents at power-up can generate a transient input voltage that
may block the lower reaches of the dynamic range until it has
become much less than the signal.
A single-sided signal may be applied via a blocking capacitor to
either Pin 1 or 8, with the other pin ac-coupled to ground. Under
these conditions, the largest input signal that can be handled is
0 dBV (a sine amplitude of 1.4 V) when using a 3 V supply; a
+5 dBV input (2.5 V amplitude) may be handled with a 5 V
supply. When using a fully-balanced drive this maximum input
level is permissible for supply voltages as low as 2.7 V. Above
10 MHz, this is easily achieved using an LC matching network.
Such a network, having an inductor at the input, usefully elimi-
nates the input transient noted above.
REV. A
INLO
INHI
C
C
C
M
P
D
COM
COM
ENBL
Figure 22. Signal Input Interface
4k
Figure 21. ENABLE Interface
2k
40k
COMM
TYP 2.2V FOR
3V SUPPLY,
3.2V AT 5V
DETECTORS
TOP-END
D
is the differential input capacitance,
E
is shut off, and the inputs float;
COMM
S
S
6k
6k
TO BIAS
STAGES
~3k
AD8310
Q1
125
Q2
I
2.4mA
E
P
and C
VPOS
M
–9–
Occasionally, it may be desirable to use the dc-coupled potential
of the AD8310, in baseband applications. The main challenge
here is to present the signal at the elevated common-mode input
level, which may require the use of low-noise, low-offset buffer
amplifiers. In some cases, it may be possible to use dual supplies
of 3 V, which allows the input pins to operate at ground poten-
tial. The output, which is internally referenced to the COMM
pin (now at –3 V), may be positioned back to ground level, with
essentially no sensitivity to the particular value of the negative
supply.
Offset Interface
The input-referred dc offsets in the signal path are nulled via the
interface associated with Pin 3, shown in Figure 23. Q1 and Q2
are the first-stage input transistors, having slightly unbalanced
load resistors, resulting in a deliberate offset voltage of about
1.5 mV referred to the input pins. Q3 generates a small current
to null this error, dependent on the voltage at the OFLT pin.
When Q1 and Q2 are perfectly matched this voltage is about
1.75 V; in practice, it will range from approximately 1 V to 2.5 V
for an input-referred offset of 1.5 mV.
In normal operation using an ac-coupled input signal, the OFLT
pin should be left unconnected. The g
when the chip is disabled, converts a residual offset (sensed at a
point near the end of the cascade of amplifiers) to a current.
This is integrated by the on-chip capacitor C
external capacitance C
back to the input stage in the polarity needed to null the output
offset. From a small-signal perspective, this feedback alters the
response of the amplifier, which exhibits a zero in its ac transfer
function, resulting in a closed-loop high-pass –3 dB corner at
about 2 MHz. An external capacitor will lower the high-pass
corner to arbitrarily low frequencies; using 1 F, the 3 dB corner
is at 60 Hz.
STAGE
INPUT
BIAS,
Figure 23. Offset Interface and Offset-Nulling Path
1.2V
Q1
125
Q2
Q3
OFLT
BALANCE
36k
16 A AT
, to generate the voltage that is applied
Q4
48k
MAIN GAIN
STAGES
OFLT
m
C
cell, which is gated off
S
OFLT
HP
g
, plus any added
m
AD8310
33pF
AVERAGE
ERROR
CURRENT
TO LAST
DETECTOR
VPOS
COMM