W90210F Winbond Electronics Corp America, W90210F Datasheet - Page 19

• Manufacturer Part Number: W90210F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

software debugging using breakpoints. The debug SFU is currently provided in the W90210F CPU core. The debug
SFU supports two sets of registers for both data breakpoints and instruction breakpoints.
queue (IIAOQ). For the data debug trap, the trapping address is stored in the interruption offset register (IOR).
to execute an instruction (including nullified instructions) at an address matching the corresponding IBAOR will cause an
instruction debug trap. If the e bit is 0, that instruction breakpoint is disabled.
1, any non-nullified load or semaphore instruction to an address matching the corresponding DBAOR will cause a data
debug trap. If the w bit is 1, any non-nullified store or semaphore instruction or cache purge operation to an address
matching the corresponding DBAOR will cause a data debug trap. If the r and w bits are both 0, the data breakpoint is
disabled.
1, the data debug trap and instruction debug trap are enabled; when 0, the traps are disabled. The G-bit is set to 0 on
interruptions.
each instruction, except for RFI and RFIR instructions which may set it to 1. When 1, data debug traps are disabled.
execution of each instruction, except for RFI and RFIR instructions which may set it to 1. When 1, instruction debug
traps are disabled.
When bit 17 is enabled, the SFU #1 instructions will operate normally, but when disabled, all SFU #1 instructions will
take an assist emulation trap.
group 3.
5.4. Debug Special Function Unit
The debug special function unit is an optional, architected SFU which provides hardware assistance for
For the instruction debug trap, the trapping address is stored in the interruption instruction address offset
The e bit in each IBAMR determines whether this instruction breakpoint is enabled. If the e bit is 1, any attempt
Instruction Breakpoint Address Offset Register (IBAOR0, IBAOR1)
Instruction Breakpoint Address Mask Register (IBAMR0, IBAMR1)
Data Breakpoint Address Offset Register (DBAOR0, DBAOR1)
Data Breakpoint Address Mask Register (DBAMR0, DBAMR1)
The r and w bits in each DBAMR determine the type of access this data breakpoint is enabled for. If the r bit is
For the control of the debug SFU, three bits are added to the PSW register.
Debug Trap Enable Bit (G)
Data Debug Trap disable Bit (Y)
Instruction Debug Trap disable Bit (Z)
In addition, CCR bits 16- 23 are used as enable/disable bits for SFUs 0- 7. The debug SFU will use bit 17.
Two new exceptions are added to the architecture- one for instruction debugging and one for data debugging.
Instruction Debug Trap (30)
Data Debug Trap (31)
Following instructions are added for the debug SFU.
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
: Interruption #31 is defined as the data debug trap. This trap belongs to group3.
: Bit 25 of the PSW is defined as the G-bit- the debug trap enable bit. When the G-bit is
0
0
e
0
0
r w
: Interruption #30 is now defined as the instruction debug trap. This trap belongs to
1
1 2
: Bit 0 of the PSW is defined as the Y-bit. The Y-bit is set to 0 after the execution of
rv
rv
: Bit 1 of the PSW is defined as the Z-bit. The Z-bit is set to 0 after the
7 8
7 8
Figure 5.12 Debug SFU registers
19
address offset
address offset
DBAOR
DBAMR
IBAMR
IBAOR
:
:
mask
:
:
mask
31
31
31
31
W90210F
Version 1.4, 10/8/97