W90210F Winbond Electronics Corp America, W90210F Datasheet - Page 10

• Manufacturer Part Number: W90210F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

DREQ0
DREQ1
DACK0
DACK1
DMARDY
CS0
CS1
DA[0:11]
IOR
IOW
TC0
TC1
DD[0:7]
ECP Interface
Busy
nFault
nAck
PError
Select
nSelectIn
nInit
nAutoFd
nStrobe
ED[0:7]
Memory Controller Interface
RAS#[0:3]
CAS#[0:3]
WE#
RCS#[0:3]
ROMEN
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
I
O
I
O
O
O
O
O
I/O
I
I
I
I
I
O
O
O
O
I/O
O
O
O
O
O
131
133
134
135
116
136
137
114-104,102
119
117
120
121
130,128-122
138
139
140
141
142
153
154
155
156
152-148,146-
145,143
201-204
195,197-198,200
205
17-18,20-21
14
10
DMA Request signals request an external transfer on DMA
channel 0 (DREQ0) or DMA channel 1 (DREQ1).
DMA Acknowledge signals acknowledge an external transfer on
DMA channel 0 (DREQ0) or DMA channel 1 (DREQ1).
DMA Device Ready signal is used to extend the length of DMA
bus cycles. If a device wants to extend the DMA bus cycles, it will
force the DMARDY signal low when it decodes its address and
receives a IOR or IOW command.
DMA Chip Select signals select the corresponding I/O devices for
programming or DMA transfers.
12-bit DMA I/O Address Bus, bit 0 is the most significant bit.
DMA I/O read signal is used to indicate to the I/O device that the
present bus cycle is an I/O read cycle.
DMA I/O write signal is used to indicate to the I/O device that the
present bus cycle is an I/O write cycle.
Terminal count for DMA channels, the pin is driven active for one
clock when byte count reaches zero and after the last transfer for
a DAM has completed.
8-bit DMA I/O Data bus, bit 0 is the most significant bit.
For more detail description of the ECP interface signals, please
refer to the
ECP busy input signal
ECP fault input
ECP acknowledge input
ECP parity error
ECP Select
ECP select output
ECP initialization
ECP Autofeed
ECP Strobe
Bi-directional ECP Data bus, ED[0] is the most significant bit
(msb).
DRAM Row Address Strobe, Banks 0-3. These signals are used
to select the DRAM row address. A High-to-Low transition on one
of these signals causes a DRAM in the corresponding bank to
latch the row address and begin an access.
DRAM Column Address Strobes, Byte 0-3. These signals are
used to select the DRAM column address. A High-to-Low
transition on these signals causes the DRAM selected by
RAS#[0:3] to latch the column address and complete the access.
DRAM Write Enable signal is used to write the selected DRAM
bank.
ROM Chip Selects, Banks 0-3. A low level on one of these signals
selects the memory devices in the corresponding ROM bank.
ROM Address Latch, ROM address are divided into two portions,
higher address bits and lower address bits, the address will be put
out on the MA bus in two consecutive cycles. The ROMEN signal
is used to latch the higher address bits in the first ROM address
cycle.
IEEE P1284 Standard
W90210F
Version 1.4, 10/8/97