STK672-630A-E Sanyo Semicon Device, STK672-630A-E Datasheet - Page 11

• Manufacturer Part Number: STK672-630A-E
• Description: 2-phase Stepping Motor Driver
• Manufacturer: Sanyo Semicon Device

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Usage Notes
1. STK672-630A-E, STK672-640A-E input signal functions and timing
[ENABLE, CLOCK and power on reset, RESETB (Input signal timing when power is first applied)]
[CLOCK (Phase switching clock)]
• Input frequency: DC to 50kHz
• Minimum pulse width: 10μs
• MODE2=1(High) Signals are read on the rising edge.
• MODE2=0(Low) Signals are read on the rising and falling edges.
[CWB (Motor direction setting)]
[ENABLE (Forcible on/off control of the A, AB, B, and BB outputs, and hybrid IC internal operation)]
The control IC of the driver is equipped with a power on reset function capable of initializing internal IC operations
when power is supplied. A 4V typ setting is used for power on reset. Because the specification for the MOSFET gate
voltage is 5V±5%, conduction of current to output at the time of power on reset adds electromotive stress to the
MOSFET due to lack of gate voltage. To prevent electromotive stress, be sure to set ENABLE=Low while V DD ,
which is outside the operating supply voltage, is less than 4.75V.
In addition, if the RESETB terminal is used to initialize output timing, be sure to allow at least 10μs until CLOCK
input.
The direction of rotation is switched by setting CWB to 1 (high) or 0 (low).
See the timing charts for details on the operation of the outputs.
Note: The state of the CWB input must not be changed during the 6.25μs period before and after the rising edge of the
ENABLE=1: Normal operation
ENABLE=0: Outputs A, AB, B, and BB forced to the off state.
If sudden stop is applied to the CLOCK signal used for motor rotation, the motor axis may advance beyond the
theoretical position due to inertia. To stop at the theoretical position, the SLOW DOWN setting for gradually slowing
the CLOCK cycle is required.
CLOCK input.
Control IC power (V DD ) rising edge
Control IC power on reset
RESETB signal input
ENABLE signal input
CLOCK signal input
If, during the state where CLOCK signal input is provided, the ENABLE pin is set to 0 and then is later
restored to the 1 state, the IC will resume operation with the excitation timing continued from before the
point ENABLE was set to 0.
ENABLE, CLOCK, and RESETB Signals Input Timing
At least 10μs
STK672-630A-E
4V typ
At least 10μs
No time specification
3.8V typ
No. A1129-11/21
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