nRF24E1 Nordic VLSI, nRF24E1 Datasheet - Page 54

• Manufacturer Part Number: nRF24E1
• Description: 2.4Ghz RF Transceiver With Embedded 8051 Compatible Microcontroller And 9 Input, 10 Bit ADC
• Manufacturer: Nordic VLSI

PRODUCT SPECIFICATION
PCON.2
PCON.1
PCON.0
Table 9-1 : PCON Register – SFR 0x87
An instruction that sets the IDLE bit (PCON.0) causes the nRF24E1 to enter idle
mode when that instruction completes. In idle mode, CPU processing is suspended
and internal registers and memory maintain their current data. However, unlike the
standard 8051, the CPU clock is not disabled internally, thus not much power is
saved.
There are two ways to exit idle mode: activate any enabled interrupt or watchdog
reset. Activation of any enabled interrupt causes the hardware to clear the IDLE bit
and terminate idle mode. The CPU executes the ISR associated with the received
interrupt. The RETI instruction at the end of the of ISR returns the CPU to the
instruction following the one that put the nRF24E1 into idle mode. A watchdog reset
causes the nRF24E1 to exit idle mode, reset internal registers, execute its reset
sequence and begin program execution at the standard reset vector address 0x0000.
An instruction that sets the STOP bit (PCON.1) causes the nRF24E1 to enter stop
mode when that instruction completes. Stop mode is identical to idle mode, except
that the only way to exit stop mode is by watchdog reset Since there is little power
saving, stop mode is not recommended, as it is more efficient to use power down
mode.
An instruction that sets the STOP_CLOCK bit (SFR 0xB6 CK_CTRL.1) causes the
nRF24E1 to enter power down mode when that instruction completes. In power down
mode, CPU processing is suspended, while internal registers and memories maintain
their current data. The CPU will perform a controlled shutdown of clock and power
regulators. But the transceiver subsystem has to be disabled separately by setting
RADIO.7=0 before stopping the clock.
The system can only be restarted from an external interrupt, an RTC wakeup interrupt
or a Watchdog reset. Activation of any enabled interrupt causes the hardware to clear
the CK_CTRL.1 bit and terminate power down mode. The CPU executes the ISR
associated with the received interrupt. The RETI instruction at the end of the of ISR
returns the CPU to the instruction following the one that put the nRF24E1 into power
down mode. A watchdog reset causes the nRF24E1 to exit power down mode, reset
internal registers, execute its reset sequence and begin program execution at the
standard reset vector address 0x0000.
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone [phone] - Fax [phone]
Revision: 1.0
GF0 – General purpose flag 0. Bit-addressable, general purpose flag for
software control.
STOP – Stop mode select. Setting the STOP bit places the nRF24E1 in
stop mode.
IDLE – Idle mode select. Setting the IDLE bit places the nRF24E1 in
idle mode.
QhtrÃ$#ÂsÃ(&
July 2003