KSZ9021GN TR Micrel Inc, KSZ9021GN TR Datasheet - Page 23

• Manufacturer Part Number: KSZ9021GN TR
• Description: Specifications: Number of Drivers/Receivers: 8/8 ; Type: Transceiver ; Voltage - Supply: 3.135 V ~ 3.465 V ; Package / Case: 64-VFQFN Exposed Pad ; Packaging: Tape & Reel (TR) ; Protocol: Gigabit Ethernet ; Lead Free Status: Lead Free ; RoHS Stat
• Manufacturer: Micrel Inc

Micrel, Inc.
MII Interface
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
In MII operation, the MII pins function as follow:
The KSZ9021GN combines GMII mode with MII mode to form GMII/MII mode to support data transfer at 10/100/1000
Mbps speeds. After the power-up or reset, the KSZ9021GN is then configured to GMII/MII mode if the MODE[3:0] strap-
in pins are set to 0001. See Strapping Options section.
The KSZ9021GN has the option to output a low jitter 125MHz reference clock on CLK125_NDO (pin 55). This clock
provides a lower cost reference clock alternative for GMII/MII MACs that require a 125MHz crystal or oscillator. The
125MHz clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.
The KSZ9021GN provides a dedicated transmit clock output pin for MII mode, defined as follow:
September 2010
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Pin count is 16 pins (7 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision
indication).
10Mbps and 100Mbps are supported at both half and full duplex.
Data transmission and reception are independent and belong to separate signal groups.
Transmit data and receive data are each 4-bit wide, a nibble.
The PHY sources the transmit reference clock, TX_CLK, at 25MHz for 100Mbps and 2.5MHz for 10Mbps.
The PHY recovers and sources the receive reference clock, RX_CLK, at 25MHz for 100Mbps and 2.5MHz for
10Mbps.
TX_EN, TXD[3:0] and TX_ER are driven by the MAC and shall transition synchronously with respect to
TX_CLK.
RX_DV, RXD[3:0], and RX_ER are driven by the KSZ9021GN and shall transition synchronously with respect to
RX_CLK.
CRS and COL are driven by the KSZ9021GN and are not required to transition synchronously with respect to
either TX_CLK or RX_CLK.
TX_CLK (output, pin 57) :
Sourced by KSZ9021GN in MII mode for 10/100Mbps speed
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KSZ9021GN