KSZ9021GN TR Micrel Inc, KSZ9021GN TR Datasheet - Page 13

• Manufacturer Part Number: KSZ9021GN TR
• Description: Specifications: Number of Drivers/Receivers: 8/8 ; Type: Transceiver ; Voltage - Supply: 3.135 V ~ 3.465 V ; Package / Case: 64-VFQFN Exposed Pad ; Packaging: Tape & Reel (TR) ; Protocol: Gigabit Ethernet ; Lead Free Status: Lead Free ; RoHS Stat
• Manufacturer: Micrel Inc

Micrel, Inc.
Note:
1. P = Power supply.
September 2010
Pin Number
PADDLE
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up.
Ipu/O = Input with internal pull-up / Output.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
CLK125_NDO /
AVDDL_PLL
LED_MODE
Pin Name
RESET_N
TX_CLK
AGNDH
AVDDH
P_GND
DVDDL
LDO_O
INT_N
MDIO
ISET
COL
XO
XI
Type
Ipu/O
Gnd
Gnd
I/O
Ipu
I/O
O
O
O
P
O
P
O
P
I
(1)
Pin Function
Management Data Input / Output
This pin is synchronous to MDC (pin 50) and requires an external pull-up resistor
to DVDDH (digital V
GMII Mode:
MII Mode:
Interrupt Output
This pin provides a programmable interrupt output and requires an external pull-up
resistor to DVDDH (digital V
Register 1Bh is the Interrupt Control/Status Register for programming the interrupt
conditions and reading the interrupt status. Register 1Fh bit 14 sets the interrupt
output to active low (default) or active high.
1.2V digital V
125MHz Clock Output
This pin provides a 125MHz reference clock output option for use by the MAC. /
Config Mode:
Chip Reset (active low)
Hardware pin configurations are strapped-in at the de-assertion (rising edge) of
RESET_N. See “Strapping Options” section for more details.
MII Mode:
On-chip 1.2V LDO Controller Output
This pin drives the input gate of a P-channel MOSFET to generate 1.2V for the
chip’s core voltages. If 1.2V is provided by the system and this pin is not used, it
can be left floating.
1.2V analog V
25MHz Crystal feedback
This pin is a no connect if oscillator or external clock source is used.
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm tolerance
3.3V analog V
Set transmit output level
Connect a 4.99KΩ 1% resistor to ground on this pin.
Analog ground
Exposed Paddle on bottom of chip
Connect P_GND to ground.
DD
DD
DD
for PLL
GMII COL (Collision Detected) Output
MII COL (Collision Detected) Output
The pull-up/pull-down value is latched as LED_MODE during
power-up / reset. See “Strapping Options” section for details.
MII TX_CLK (Transmit Reference Clock) Output
DD
13
) in a range from 1.0KΩ to 4.7KΩ.
DD
) in a range from 1.0KΩ to 4.7KΩ when active low.
M9999-091010-1.1
KSZ9021GN