AL4CS241 AverLogic Technologies, Inc., AL4CS241 Datasheet - Page 12

• Manufacturer Part Number: AL4CS241
• Manufacturer: AverLogic Technologies, Inc.

9.0 Multiple Devices Bus Expansion and Cascading
9.1 Width Expansion Configuration
Simply connecting the corresponding input controls signals of multiple devices may increase data bus
width. A composite flag should be created for each of the end-point status flags (/EF and /FF). The
partial status flags (/PAE and /PAF) can be detected from any one device. Figure 15 demonstrates an
18-bit word width data bus by using two AL4CS211/221/231/241/251s. Any word width expansion
can be attained by adding additional AL4CS211/221/231/241/251s. When these devices are in a
Width Expansion Configuration, the Read Enable 2 (/REN2) control input can be grounded (see
Figure 15). In this configuration, theWriteEnable2<Load> (WEN2</LD>) pin is set LOW at Reset so
that the pin operates as a control to load and read the programmable flag offsets.
9.2 Depth Expansion
The depth expansion of AL4CS211/221/231/241/251 is also possible. The existence of two enable
pins on the read and write port allow depth expansion. The Write Enable 2<Load> pin is used as a
second write enable in a depth expansion configuration thus the programmable flags are set to the
default values. Depth expansion is possible by using one enable input for system control while the
other enable input is controlled by expansion logic to direct the flow of data. A typical application
would have the expansion logic alternate data access from one device to the next in a sequential
manner. These FIFOs operate in the Depth Expansion configuration when the following conditions
are met:
AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
18-Bit Data In Bus
Full Flag/
Input Ready
Programmable
Write Controls
Write Enable
Write Enable2
Write Clock
Figure 2. Multiple FIFO memory
WCLK
/WEN1
WEN2
/PAE
AL4CS2x1
with programmable flags used in depth expansion configuration
/REN1
Read Controls
Q[8:0]
RCLK
/PAF
/OE
AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
Write Controls
WCLK
/WEN1
WEN2
/PAE
AL4CS2x1
/REN1
RCLK
Q[8:0]
/PAF
/OE
December 14, 2001
18-Bit Data Out Bus
Output Enable
Read Enable
Programmable
Read Clock
Read Controls
Output Ready
Empty Flag/
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