AL4CS241 AverLogic Technologies, Inc., AL4CS241 Datasheet - Page 10

• Manufacturer Part Number: AL4CS241
• Manufacturer: AverLogic Technologies, Inc.

8.2.6 Output Enable (/OE)
When Output Enable (/OE) is enabled (LOW), the parallel output buffers receive data from the output
register. When /OE is disabled (HIGH), the Q8 ~ Q0 output data bus is in a high-impedance state.
8.2.7 Write Enable2 & /LD (WEN2</LD>)
This is a dual-purpose pin. The FIFO can be configured at Reset to have programmable flags or to
have two write enables, which allows depth expansion.
2 Write Enable Configuration
If Write Enable 2<Load> (WEN2</LD>) is set high at Reset (/RS = LOW), this pin operates as a
second Write Enable pin. In this configuration, when Write Enable (/WEN1) is LOW and Write
Enable 2<Load> (WEN2</LD>) is HIGH, data can be written into the FIFO on the rising edge of
every Write Clock (WCLK). Data is stored in FIFO sequentially and independently of any on-going
read operation. When Write Enable (/WEN1) is HIGH and/or Write Enable 2<Load> (WEN2</LD>)
is LOW, the input register holds the previous data and no new data is allowed to be written into the
FIFO. To prevent data overflow, the Full Flag (/FF) will go LOW, inhibiting further write operations.
Upon the completion of a valid read cycle, the Full Flag (/FF) will go HIGH after t
write to begin. Write Enable 1 (/WEN1) and Write Enable 2<Load> (WEN2</LD>) are ignored
when the FIFO is full.
Single Write Enable and Programmable Flags Support Configuration
The FIFO is configured to have programmable flags when the Write Enable2<Load> (WEN2</LD>)
is set to LOW at Reset (/RS = LOW). The AL4CS211/221/231/241/251 devices contain four 8-bit
offset registers, which can be loaded with data on the inputs, or read from the outputs. See following
table for details of the size of the registers and the default values.
In this configured, when the Write Enable1 (/WEN1) and Write Enable 2<Load> (WEN2</LD>) are
set LOW, data on the inputs D8 ~ D0 is written into the Empty (Least Significant Bit) Offset register
on the first rising edge of the Write Clock (WCLK). Data is written into the Empty (Most Significant
Bit) Offset register on the second rising edge of the Write Clock (WCLK), into the Full (Least
Significant Bit) Offset register on the third transition, and into the Full (Most Significant Bit) Offset
register on the fourth transition. The fifth transition of the Write Clock (WCLK) again writes to the
Empty (Least Significant Bit) Offset register.
AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
AL4CS211
AL4CS221
AL4CS231
AL4CS241
AL4CS251
[7:0] Empty Offset (LSB)
[7:0] Empty Offset (LSB)
[7:0] Empty Offset (LSB)
[7:0] Empty Offset (LSB)
[7:0] Empty Offset (LSB)
Default = 07h
Default = 07h
Default = 07h
Default = 07h
Default = 07h
1
st
word
[1:0] Empty Offset (MSB)
[2:0] Empty Offset (MSB)
[3:0] Empty Offset (MSB)
[4:0] Empty Offset (MSB)
[0] Empty Offset (MSB)
Default = 00000b
Default = 0000b
Default = 000b
Default = 00b
Default = 0b
2
nd
word
AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
[7:0] Full Offset (LSB)
[7:0] Full Offset (LSB)
[7:0] Full Offset (LSB)
[7:0] Full Offset (LSB)
[7:0] Full Offset (LSB)
Default = 07h
Default = 07h
Default = 07h
Default = 07h
Default = 07h
3
rd
word
WFF
December 14, 2001
[1:0] Full Offset (MSB)
[2:0] Full Offset (MSB)
[3:0] Full Offset (MSB)
[4:0] Full Offset (MSB)
, allowing a valid
[0] Full Offset (MSB)
Default = 00000b
Default = 0000b
Default = 000b
Default = 00b
Default = 0b
4
th
word
10