ADSP-21065 Analog Devices, ADSP-21065 Datasheet - Page 22

• Manufacturer Part Number: ADSP-21065
• Description: DSP Microcomputer
• Manufacturer: Analog Devices

ADSP-21065L
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between multiprocessing ADSP-21065Ls (BRx) or a host processor (HBR,
HBG).
Parameter
Timing Requirements:
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
HBGRCSV
SHBRI
HHBRI
SHBGI
HHBGI
SBRI
HBRI
DHBGO
HHBGO
DBRO
HBRO
DCPAO
TRCPA
DRDYCS
TRDYHG
ARDYTR
For first asynchronous access after HBR and CS asserted, ADDR
low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the Host Processor Control of the ADSP-21065L section of the
ADSP-21065L SHARC User’s Manual, Second Edition.
Only required for recognition in the current cycle.
CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
(O/D) = open drain, (A/D) = active drive.
HBG Low to RD/WR/CS Valid
HBR Setup Before CLKIN
HBR Hold Before CLKIN
HBG Setup Before CLKIN
HBG Hold Before CLKIN High
BRx, CPA Setup Before CLKIN
BRx, CPA Hold Before CLKIN High
HBG Delay After CLKIN
HBG Hold After CLKIN
BRx Delay After CLKIN
BRx Hold After CLKIN
CPA Low Delay After CLKIN
CPA Disable After CLKIN
REDY (O/D) or (A/D) Low from CS and HBR Low
REDY (O/D) Disable or REDY (A/D) High from HBG
REDY (A/D) Disable from CS or HBR High
2
2
1
3
23-0
must be a nonMMS value 1/2 t
4
4
4
CK
before RD or WR goes low or by t
Min
12.0 + 12 DT
6.0 + 8 DT
7.0 + 8 DT
1.0 – 2 DT
1.0 – 2 DT
1.0 – 2 DT
44.0 + 43 DT
Max
20.0 + 36 DT
6.0 + 12 DT
1.0 + 8 DT
1.0 + 8 DT
8.0 – 2 DT
7.0 – 2 DT
11.5 – 2 DT
5.5 – 2 DT
13.0
10.0
HBGRCSV
after HBG goes
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns