ADSP-21065 Analog Devices, ADSP-21065 Datasheet - Page 13

• Manufacturer Part Number: ADSP-21065
• Description: DSP Microcomputer
• Manufacturer: Analog Devices

POWER DISSIPATION ADSP-21065L
These specifications apply to the internal power portion of V
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note SHARC Power Dissipation Measurements.
Specifications are based on the following operating scenarios:
Operation
Instruction Type
Instruction Fetch
Core Memory Access
Internal Memory DMA
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK × I
Parameter
I
I
I
I
I
NOTES
1
2
3
4
5
TIMING SPECIFICATIONS
General Notes
Two speed grades of the ADSP-21065L are offered, 60 MHz and 66 MHz instruction rates. The specifications shown are based on a
CLKIN frequency of 30 MHz (t
max range of the t
period of 33.3 ns:
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addi-
tion or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical varia-
tions and worst cases. Consequently, you cannot meaningfully add parameters to derive longer times.
See Figure 27 in Equivalent Device Loading for AC Measurements (Includes All Fixtures) for voltage reference levels.
The test program used to measure I
power measurements made using typical applications are less than specified.
I
I
IDLE denotes ADSP-21065L state during execution of IDLE instruction.
IDLE16 denotes ADSP-21065L state during execution of IDLE16 instruction.
DDINPEAK
DDINHIGH
DDINLOW
DDIDLE
DDIDLE16
DDINHIGH
DDINLOW
is a composite average based on a range of low activity code.
is a composite average based on a range of high activity code.
DDINPEAK
CK
+ %HIGH × I
specification; see Clock Input below). DT is the difference between the actual CLKIN period and a CLKIN
Supply Current (Internal)
Supply Current (Internal)
Supply Current (Internal)
Supply Current (IDLE)
Supply Current (IDLE16)
DDINPEAK
CK
Peak Activity
(I
Multifunction
Cache
2 per Cycle (DM and PM)
1 per Cycle
DDINHIGH
DDINPEAK
= 33.3 ns). The DT derating allows specifications at other CLKIN frequencies (within the min–
represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
Table III. Internal Current Measurement Scenarios
+ %LOW × I
)
Table II. Internal Current Measurements
4
1
2
3
5
DT = (t
DDINLOW
DD
only. See the Power Dissipation section of this data sheet for calcula-
CK
Test Conditions
t
t
t
t
t
t
t
t
V
CK
CK
CK
CK
CK
CK
CK
CK
+ %IDLE16 × I
DD
– 33.3)/32
High Activity
(I
Multifunction
Internal Memory
1 per Cycle (DM)
1 per 2 Cycles
= 33 ns, V
= 30 ns, V
= 33 ns, V
= 30 ns, V
= 33 ns, V
= 30 ns, V
= 33 ns, V
= 30 ns, V
DDINHIGH
= max
)
DD
DD
DD
DD
DD
DD
DD
DD
DDIDLE16
= max
= max
= max
= max
= max
= max
= max
= max
= POWER CONSUMPTION
Max
470
510
275
300
240
260
150
155
50
Low Activity (I
Single Function
Internal Memory
None
1 per 2 Cycles
ADSP-21065L
DDINLOW
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
)