ADSP-21061 Analog Devices, ADSP-21061 Datasheet - Page 28

• Manufacturer Part Number: ADSP-21061
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

Parameter
Read Cycle
Timing Requirements:
t
t
t
t
t
Switching Characteristics:
t
t
t
t
Write Cycle
Timing Requirements:
t
t
t
t
t
t
t
t
t
t
Switching Characteristics:
t
t
t
NOTES
1
2
Asynchronous Read/Write—Host to ADSP-21061
Use these specifications for asynchronous host processor accesses
of an ADSP-21061, after the host has asserted CS and HBR
(low). After HBG is returned by the ADSP-21061, the host can
SADRDL
HADRDH
WRWH
DRDHRDY
DRDHRDY
SDATRDY
DRDYRDL
RDYPRD
HDARWH
SCSWRL
HCSWRH
SADWRH
HADWRH
WWRL
WRWH
DWRHRDY
SDATWH
SDATWH
HDATWH
DRDYWRL
RDYPWR
SRDYCK
Not required if RD and address are valid t
This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at t
ADSP-21061/ADSP-21061L
or WR goes low or by t
sor Control of the ADSP-2106x section in the ADSP-2106x SHARC User’s Manual, Second Edition.
same name.
(50 MHz) Data Setup before WR High, t
Address Setup/CS Low before RD Low
Address Hold/CS Hold Low after RD
RD/WR High Width
RD High Delay after REDY (O/D) Disable
RD High Delay after REDY (A/D) Disable
Data Valid before REDY Disable from Low
REDY (O/D) or (A/D) Low Delay after RD Low
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable after RD High
CS Low Setup before WR Low
CS Low Hold after WR High
Address Setup before WR High
Address Hold after WR High
WR Low Width
RD/WR High Width
WR High Delay after REDY (O/D) or (A/D) Disable
Data Setup before WR High
Data Hold after WR High
REDY (O/D) or (A/D) Low Delay after WR/CS Low
REDY (O/D) or (A/D) Low Pulsewidth for Write
REDY (O/D) or (A/D) Disable to CLKIN
HBGRCSV
after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the Host Proces-
REDY (A/D)
REDY (O/D)
HBGRCSV
CLKIN
after HBG goes low. For first access after HBR asserted, ADDR
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
CK
= 20 ns
1
2
CK
drive the RD and WR pins to access the ADSP-21061’s internal
memory or IOP registers. HBR and HBG are assumed low for
this timing.
< 25 ns. For all other devices, use the preceding timing specification of the
Min
0
0
6
0
0
45 + DT
2
0
0
5
2
8
6
0
3
2.5
1
1 + 7DT/16
2
15
ADSP-21061 (5 V)
t
SRDYCK
Max
10
8
11
8 + 7DT/16
31-0
must be a non-MMS value 1/2 t
Min
0
0
6
0
0
2
45 + DT
2
0
0
5
2
8
6
0
3
1
15
1 + 7DT/16
ADSP-21061L (3.3 V)
Max
13.5
8
13.5
8 + 7DT/16 ns
CLK
before RD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns