AD1981B Analog Devices, AD1981B Datasheet - Page 26

• Manufacturer Part Number: AD1981B
• Description: AD1981B AC'97 SoundMAX® Codec
• Manufacturer: Analog Devices

AD1981B
MADST
MADPD
2CMIC
FMXE
DAM
LODIS
MSPLT
DACZ
S[7:0] This register is ASCII encoded to “A.”
F[7:0] This register is ASCII encoded to “D.”
T[7:0] This register is ASCII encoded to “S.”
REV[7:0] Vendor Specific revision number: The AD1981B assigns 74h to this field.
ID1
1
1
0
0
Note that internally, the ID pins have weak pull-ups and are inverted.
Reg
No. Name
7Ch Vendor ID1 F7
Reg
No. Name
7Eh Vendor ID2 T7 T6
ID0
1
0
1
0
Mixer ADC Status Bit. Indicates status of mixer digitizing ADC (left and right channels).
0 = Mixer ADC not ready.
1 = Mixer ADC ready.
Mixer ADC Power Down. Controls power down for mixer digitizing ADC.
0 = Mixer ADC is powered on (default).
1 = Mixer ADC is powered down.
2-Channel MIC Select. This bit enables simultaneous recording from MIC1 and MIC2 inputs for applications that
use a stereo microphone array. Note that this register works in conjunction with the MS bit in Register 20h.
0 = MIC1 or MIC2 (determined by MS bit) is routed to the record selector’s left and right MIC channels as well
as to the mixer (reset default).
1 = MIC1 is routed to the record selector’s left MIC channel and MIC2 is routed to the record selector’s
right MIC channel. Note that in this mode the MS bit should be set low and MIC1 can still be enabled into the mixer.
Front DAC into Mixer Enable. Controls the front (main) DAC to mixer mute switches.
0 = Front DAC outputs are allowed to sum into the mixer (reset default).
1 = Front DAC outputs are muted into the mixer (blocked).
Digital Audio Mode. PCM DAC outputs bypass the analog mixer and are sent directly to the codec output.
Line_out Disable. Disables the Line_out pins (L/R), placing them into High Z mode so that the assigned output
audio jack can be shared for input function (or other function).
0 = Line_out pins have normal audio drive capability (reset default).
1 = Line_out pins are placed into High Z mode.
Mute Split. Allows separate mute control bits for master, headphone, line_in, CD, AUX, and PCM volume control
registers as well as record gain register.
0 = Both left and right channel mutes are controlled by Bit 15 in the respective registers (reset default).
1 = Bit 15 affects only the left channel mute and Bit 7 affects only the right channel mute.
DAC Zero-Fill. Determines DAC data fill under starved conditions.
0 = DAC data is repeated when DACs are starved for data (reset default).
1 = DAC is zero-filled when DACs are starved for data.
D15 D14 D13 D12 D11 D10 D9 D8 D7
D15 D14 D13
F6
T5 T4 T3
Codec ID
(00) Primary
(01) Secondary
(00) Primary
(00) Primary
F5
D12 D11
F4
Codec ID and External Clock Selection Table
Vendor ID Register (Index 7Ch – 7Eh)
T2
F3
T1 T0 REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 5374h
D10 D9
F2
Codec Clocking Source
24.576 MHz
12.288 MHz
48.000 MHz
F1
14.31818 MHz
–26–
D8
F0
D6
D7
S7
D5
D6
S6
(Local Xtal or External into XTL_IN)
(External into Bit_Clk)
(External into XTL_IN)
(External into XTL_IN)
D4
D5
S5
D3
D4
S4
D2
D3
S3
D2 D1 D0 Default
S2
D1
S1
D0
S0
Default
4144h
REV. A