AD1981B Analog Devices, AD1981B Datasheet - Page 22

• Manufacturer Part Number: AD1981B
• Description: AD1981B AC'97 SoundMAX® Codec
• Manufacturer: Analog Devices

AD1981B
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the
BCA bits in the EQ CNTRL Register (60h). Data will be written to memory only if the EQM bit (Register 60h, Bit 15) is asserted.
CFD[15:0]
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
RMG[3:0]
RM
LMG[3:0]
MXM
Reg. 76h
MSPLT* D15 WRITE READBACK Function
0
0
0
1
1
1
*For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate mute bits for the left and right
x is a wild card and has no effect on the value.
Reg
No. Name
62h EQ DATA CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h
Reg
No. Name
64h Mixer
channels. If MSPLT is not set, the RM bit has no effect. All registers not shown and bits containing an X are assumed to be reserved. Refer to Table VII for examples.
channels. If MSPLT is not set, RM bit has no effect.
Volume
0
0
1
0
1
1
D15
D15
MXM X
Right Mixer Gain Control. This register controls the gain into the mixer ADC from 0 dB to a maximum gain of
22.5 dB. The least significant bit represents 1.5 dB.
Right Channel Mute. Once enabled by the MSPLT bit in Register 76h, this bit mutes the right channel separately
from the MXM bit. Otherwise, this bit will always read “0” and will have no affect when set to “1.”
Left Mixer Gain Control. This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of 22.5 dB.
The least significant bit represents 1.5 dB.
Mixer Gain Register Mute.
0 = Unmuted.
1 = Muted (reset default).
Coefficient Data. The biquad coefficients are fixed point format values with 16 bits of resolution. The CFD15 bit is
the MSB, and the CFD0 bit is the LSB.
1111
0000
xxxx
1111
xxxx
xxxx
D14
Left Channel Mixer Gain D[11:8]
D14
D13
X
1111
0000
xxxx
1111
xxxx
xxxx
D13
X
D12
D12
D11
LMG3 LMG2
Table VII. Settings for Mixer ADC, Input Gain
Mixer ADC, Input Gain Register (Index 64h)
D11
22.5 dB Gain
0 dB Gain
– dB Gain, Muted
22.5 dB Gain
– dB Gain, Left Only Muted 0
– dB Gain, Left Muted
D10
EQ Data Register (Index 62h)
Mixer ADC, Input Gain (64h)
D10
D9
LMG1 LMG0 RM* X
D9
Control Bits
–22–
D8
D8
D7
D7
D7* WRITE READBACK Function
x
x
x
1
1
D6
D6
D5
X
1111
0000
xxxx
xxxx
1111
xxxx
D5
Right Channel Mixer Gain D[3:0]
D4
X
D4
D3
RMG3 RMG2 RMG1
1111
0000
xxxx
xxxx
1111
xxxx
D3
D2
D2
D1
22.5 dB Gain
0 dB Gain
– dB Gain, Muted
– dB Gain,
Right Only Muted
22.5 dB Gain
– dB Gain,
Right Muted
D1
D0
RMG0 8000h
D0
REV. A
Default
Default