AD1954 Analog Devices, AD1954 Datasheet - Page 28

• Manufacturer Part Number: AD1954
• Description: SigmaDSP Digital Audio Processor
• Manufacturer: Analog Devices

AD1954
Byte 0
00000, Wb/R, adr[9:8]
NOTES
1. ProgCount[8:0] = value of program counter where trap occurs (see table 6.1).
2. RegSel[1:0] selects one of four registers (see Data Capture Register section).
Byte 0
00000, Wb/R, adr[9:8]
NOTES
1. ProgCount[8:0] = value of program counter where trap occurs (see table 6.1).
2. RegSel[1:0] selects one of four registers (see Data Capture Register section).
Byte 0
00000, Wb/R, adr[9:8]
Byte 0
00000, Wb/R, adr[9:8]
INITIALIZATION
Power-up Sequence
The AD1954 has a built in power-up sequence that initializes
the contents of all internal RAMs. During this time, the contents
of the internal program Boot ROM are copied to the internal
Program RAM memory, and likewise the SPI Parameter RAM
is filled with values from its associated boot ROM. The data
memories are also cleared during this time.
The boot sequence lasts for 1024 MCLK cycles and starts on
the rising edge of the RESETB pin. Since the boot sequence
requires a stable master clock, the user should avoid writing to
or reading from the SPI registers during this period of time.
Note that the default power-on state of the internal clock mode
circuitry is 512 × f
rates. This mode bypasses all the internal clock doublers, and
allows the external master clock to directly operate the DSP
core. If the external master clock is 256 × f
boot sequence will operate at this reduced clock rate and take
slightly longer to complete. After the boot sequence has finished,
the clock modes may be set via the SPI port. For example, if the
external master clock frequency is 256 × f
sequence would take 1024 256 × f
after which an SPI write could occur to put the AD1954 in
256 × f
The default state of the MCLK input selector is MCLK0. Since
this input selector is controlled using the SPI port, and the SPI
port cannot be written to until the boot sequence is complete,
there must be a stable master clock signal present on the MCLK0
pin at start-up.
S
mode.
Table XVII. Data_Capture_Serial Out Register (Address and Register Select) WRITE Format
S
, or about 24 MHz for normal audio sample
Byte 1
adr[7:0]
Byte 1
adr[7:0]
PRELIMINARY TECHNICAL DATA
S
clock cycles to complete,
Byte 1
adr[7:0]
Byte 1
adr[7:0]
Table XVI. Data Capture Register WRITE Format
S
Byte 2
Byte 2
00000000
paramAdr[7:0]
or 384 × f
S
Table XIX. Safeload Register Write Format
Table XVIII. Data Capture READ Format
clock, the boot
S
, then the
Byte 2
00000, progCount[8:6]
Byte 2
00000, progCount[8:6]
Byte 3
data[23:16]
Byte 3
00, param[21:16]
Setting the Clock Mode
The AD1954 contains two clock doubler circuits that are used
to generate an internal 512 × f
either 256 × f
bits 3:2 of Control Register 2.
When the clock mode is changed, it is possible that a glitch will
occur on the internal MCLK signal. This may cause the proces-
sor to inadvertently write an incorrect value into the data RAM,
which could cause an audio pop or click sound. To prevent this,
it is recommended that the following procedure be followed:
1. Assert the soft power-down bit (Bit 6 in Control Register 1)
2. Write the desired clock mode into bits 3:2 of
3. Wait at least 1 ms while the clock doublers settle.
4. De-assert the soft power-down bit.
An alternative procedure is to initiate a “soft shutdown” of the
processor core by writing a 1 to the “halt program” bit in Con-
trol Register 1. This initiates a volume ramp-down sequence
followed by a shutdown of the DSP core. Once the core is shut
down (which can be verified by reading bit 1 from Control
Register 1, or by waiting at least 20 ms), the new clock mode
can be programmed by writing to bits <3:2> of Control Register 2.
The DSP core can then be restarted by clearing the “halt pro-
gram” bit in Control Register 1.
to stop the internal MCLK.
Control Register 2.
S
or 384 × f
Byte 4
data[15:8]
Byte 4
param[15:8]
S
. The clock mode is set by writing to
S
clock when the external clock is
Byte 3
progCount[5:0], regSel[1:0]
Byte 3
progCount[5:0], regSel[1:0]
Byte 5
data[7:0]
Byte 5
param[7:0]