AD1954 Analog Devices, AD1954 Datasheet - Page 21

• Manufacturer Part Number: AD1954
• Description: SigmaDSP Digital Audio Processor
• Manufacturer: Analog Devices

Register Bits
11
10
9
8
7
6
5:4
3:2
1:0
Register Bits
1
0
Bit 0 is asserted when all requested safeload registers have been
transferred to the parameter RAM. It is cleared after the read
operation is complete.
Bit 1 is asserted after the requested shutdown of the DSP is
completed. When this bit is set, the user is free to write or read
any RAM location without causing an audio pop or click.
Table III. Control Register 1 WRITE Definition
Table IV. Control Register 1 READ Definition
Function
De-emphasis/Aux. Serial Input Pin Select
(1 = Aux. Serial Input)
Halt Program (1 = Halt)
Initiate safe transfer (1 = transfer)
Enable DCSOUT output pin (1 = enable)
Soft Mute (1 = start mute sequence)
Soft Power down (1 = power down)
De-emphasis curve select
00 = none
01 = 44.1 kHz
10 = 32 kHz
11 = 48 kHz
Serial In Mode
00 = I
01 = Right-Justified
10 = DSP
11 = Left-Justified
Wordlength
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
Function
DSP core shutdown complete
1 = shutdown complete
0 = not shut down
Safe Memory Load Complete
1 = complete (note: cleared after read)
0 = not complete
2
S
PRELIMINARY TECHNICAL DATA
Register Bits
8
7:6
5:4
3:2
1:0
Control Register 2
Table V documents the contents of Control Register 2. bits
<1:0> set the frequency of the MCLKO pin. If these bits are set
to 00, then the MCLKO pin is disabled (default). When set to
01, the MCLKO pin is set to 512 × f
internal master clock used by the DSP core. When set to 10,
this pin is set to 256 × f
clock by 2. When set to 11, the MCLKO pin mirrors the selected
MCLK input pin (it’s the output of the MCLK MUX selector).
Note that the internal DSP master clock may either be the same
as the selected MCLK pin (when MCLK Frequency Select is set
to 512 × f
internal clock doublers (when MCLK Frequency Select is set to
256 × f
Bits <3:2> select one of three possible MCLK input frequencies.
When set to 00 (default), the MCLK frequency is set to 512 × f
this mode, the internal DSP clock and the external MCLK are at
the same frequency. When set to 01, the MCLK frequency is set to
256 × f
clock. When set to 11, the MCLK frequency is set to 384 × f
a divide-by-three and two internal clock doublers are used to gener-
ate the internal 512 × f
Bits <5:4> select one of three clock input sources using an inter-
nal MUX. To avoid click and pop noises when switching MCLK
sources, it is recommended that the user put the DSP core in
shutdown before switching MCLK sources.
Bits <7:6> select one of three serial input sources using an inter-
nal MUX. Each source selection includes a separate SDATA,
LRCLK and BCLK input. To avoid click and pop noises when
switching serial sources, it is recommended that the user put the
DSP core in shutdown before writing to these bits.
S
S
, and an internal clock doubler is used to generate the DSP
Table V. Control Register 2 WRITE Definition
or 384 × f
S
mode) or may be derived from the MCLK pin using
S
Function
Serial Port Output Enable
1 = enabled
0 = disabled
Serial Port Input Select
00 = IN0
01 = IN1
10 = IN2
11 = NA
MCLK Input Select
00 = MCLK0
01 = MCLK1
10 = MCLK2
11 = NA
MCLK In Frequency Select
00 = 512 × f
01 = 256 × f
10 = Not Available
11 = 384 × f
MCLK Out Frequency Select
00 Disabled
01 512 × f
10 256 × f
11 MCLK_out = MCLK_In (feed-thru)
mode).
S
DSP clock.
S
, derived by dividing the internal DSP
S
S
S
S
S
S
, which is the same as the
AD1954
S
, and
S
. In