AD1837 Analog Devices, AD1837 Datasheet - Page 21

• Manufacturer Part Number: AD1837
• Description: 2 ADC, 8DAC 96 Khz, 24-Bit Sigma Delta Codec
• Manufacturer: Analog Devices

CASCADE MODE
Dual AD1837Cascade
The AD1837 can be cascaded to an additional AD1837 which,
in addition to six external stereo ADCs, can be used to create a
32-channel audio system with 16 inputs and 16 outputs. The
cascade is designed to connect to a SHARC DSP and operates
in a Time Division Multiplexing (TDM) format. Figure 14
shows the connection diagram for cascade operation. The digital
interface for both parts must be set to operate in Auxiliary
512 mode by programming ADC Control Register II. AD1837
#1 is set as a master device by connecting the M/S pin to DGND
and AD1837 #2 is set as a slave device by connecting the M/S to
DVDD. Both devices should be run from the same MCLK and
PD/RST signals to ensure that they are synchronized.
REV. PrA
(SLAVE)
SHARC
ABCLK
TFSx/
DTx
DRx
RFSx
RCLKx
TCLKx
DTx
DRx
RFSx
TFSx
DRx
DTx
PRELIMINARY TECHNICAL DATA
L1
L1
AUX ADC
(SLAVE)
L2
L2
MSB
MSB
ASDATA
ALRCLK
ABCLK
L3
L3
AD1837 #1 DACs
AD1837 #1 ADCs
MSB-1
256 ABCLKs
MSB-1
L4
L4
AUX ADC
(SLAVE)
Figure 15. Cascade Timing
R1
R1
32 ABCLKs
Figure 14. Cascade
R2
R2
LSB
LSB
AD1837 #1
(MASTER)
AUX ADC
R3
(SLAVE)
R3
DSDATA
–21–
R4
R4
DON’ T CARE
With Device 1 set as a master it will generate the frame-sync and
bit clock signals. These signals are sent to the SHARC and
Device 2 ensuring that both know when to send and receive data.
The cascade can be thought of as two 256-bit shift registers,
one for each device. At the beginning of a sample interval the
shift registers contain the ADC results from the previous sample
interval. The first shift register (Device 1) clocks data into the
SHARC and also clocks in data from the second shift register
(Device 2). While this is happening, the SHARC is sending
DAC data to the second shift register. By the end of the sample
interval all 512 bits of ADC data in the shift registers will have
been clocked into the SHARC and been replaced by DAC data
which is subsequently written to the DACs. Figure 15 shows
the timing diagram for the cascade operation.
L1
L1
L2
L2
AUX ADC
(SLAVE)
L3
L3
AD1837 #2 DACs
AD1837 #2 ADCs
256 ABCLKs
ASDATA
L4
ALRCLK
ABCLK
L4
R1
R1
AUX ADC
(SLAVE)
R2
R2
R3
R3
AD1837 #2
R4
R4
AUX ADC
(SLAVE)
(SLAVE)
DSDATA
AD1837