AD1837 Analog Devices, AD1837 Datasheet - Page 11

• Manufacturer Part Number: AD1837
• Description: 2 ADC, 8DAC 96 Khz, 24-Bit Sigma Delta Codec
• Manufacturer: Analog Devices

FUNCTIONAL OVERVIEW
ADCs
There are two ADC channels in the AD1837, configured as a
stereo pair. Each ADC has fully differential inputs. The ADC
section can operate at a sample rate of up to 96 kHz. The ADCs
include on-board digital decimation filters with 120 dB stop band
attenuation and linear phase response, operating at an over-
sampling ratio of 128 (for 48 kHz operation) or 64 (for 96 kHz
operation).
ADC peak level information for each ADC may be read from
the ADC Peak 0 and ADC Peak 1 registers. The data is sup-
plied as a 6-bit word with a maximum range of 0 dB to –63 dB
and a resolution of 1 dB. The registers will hold peak informa-
tion until read; after reading, the registers are reset so that new
peak information can be acquired. Refer to the register descrip-
tion for details of the format. The two ADC channels have a
common serial bit clock and a left-right framing clock. The
clock signals are all synchronous with the sample rate.
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the M/S pin to
ODVDD or DGND respectively. When the pins are set as
outputs, the AD1837 will generate the timing signals. When
the pins are set as inputs, the timing must be generated by the
external audio controller.
DACs
The AD1837 has eight DAC channels arranged as four indepen-
dent stereo pairs, with eight single-ended analog outputs for
improved noise and distortion performance. Each channel has
its own independently programmable attenuator, adjustable in
1024 linear steps. Digital inputs are supplied through four serial
data input pins (one for each stereo pair) and a common frame
(DLRCLK) and bit (DBLCK) clock. Alternatively, one of the
“packed data” modes may be used to access all eight channels
on a single TDM data pin. A Stereo Replicate feature is included
where the DAC data sent to the first DAC pair is also sent to
the other DACs in the part. The AD1837 can accept DAC data
at a sample rate of 192 kHz on DAC 1 only. The stereo repli-
cate feature can then be used to copy the audio data to the other
DACs.
Each set of differential output pins sits at a dc level of V
swings ± 1.4 V for a 0 dB digital input signal. A single op amp
third-order external low-pass filter is recommended to remove
high-frequency noise present on the output pins, as well as to
provide differential-to-single-ended conversion. Note that the use
of op amps with low slew rate or low bandwidth may cause
high-frequency noise and tones to fold down into the audio
band; care should be exercised in selecting these components.
REV. PrA
PRELIMINARY TECHNICAL DATA
REF
, and
–11–
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases this capacitor may be eliminated with little effect on
performance.
DAC and ADC Coding
The DAC and ADC output data stream is in a two’s comple-
ment encoded format. The word width can be selected from
16-bit, 20-bit, or 24-bit. The coding scheme is detailed in
Table I.
Code
01111......1111
00000......0000
10000......0000
Clock Signals
The DAC and ADC engines in the AD1837 are designed to
operate from a 24.576 MHz Internal Master Clock (IMCLK).
This clock is used to generate 48 kHz and 96 kHz sampling on
the ADC and 48 kHz, 96 kHz and 192 kHz on the DAC,
although the 192 kHz option is only available on one DAC
pair. The Stereo Replicate feature can be used to copy this
DAC data to the other DACs if required.
To facilitate the use of different MCLK values the AD1837
provides a clock scaling feature. The MCLK scaler can be
programmed via the SPI port to scale the MCLK by a factor of
1 (passthrough), 2 (doubling), or scaling by a factor of 2/3. The
default setting of the MCLK scaler is 2, which will generate
48 kHz sampling from a 12.288 MHz MCLK. Additional
sample rates can be achieved by changing the MCLK value.
For example, the CD standard sampling frequency of 44.1 kHz
can be achieved using an 11.2896 kHz MCLK. Figure 2 shows
the internal configuration of the clock scaler and converter engines.
To maintain the highest performance possible, it is recommended
that the clock jitter of the master clock signal be limited to less
than 300 ps rms, measured using the edge-to-edge technique.
Even at these levels, extra noise or tones may appear in the
DAC outputs if the jitter spectrum contains large spectral peaks.
It is highly recommended that the master clock be generated by
an independent crystal oscillator. In addition, it is especially
important that the clock signal should not be passed through an
FPGA or other large digital chip before being applied to the
AD1837. In most cases this will induce clock jitter due to the
fact that the clock signal is sharing common power and ground
connections with other unrelated digital output signals.
Table I. Coding Scheme
0 (Ref Level)
Level
+FS
–FS
AD1837