ADS7807 Burr-Brown Corporation, ADS7807 Datasheet - Page 10

• Manufacturer Part Number: ADS7807
• Description: Low-Power 16-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

SERIAL OUTPUT
Data can be clocked out with the internal data clock or an
external data clock. When using serial output, be careful
with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as
these pins will come out of Hi-Z state whenever CS (pin 23)
is LOW and R/C (pin 22) is HIGH. The serial output can not
be tri-stated and is always active. Refer to the Applications
Information section for specific serial interfaces.
TABLE VI. Conversion and Data Timing. T
FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW).
SYMBOL
CS or R/C
DATACLK
NOTE: (1) If controlling with CS, tie R/C LOW. Data bus pins will remain Hi-Z at all times.
If controlling with R/C, tie CS LOW. Data bus pins will be active when R/C is HIGH, and should be left unconnected.
t
7
t
t
t
t
t
t
t
t
t
t
t
t
t
SDATA
t
t
t
t
t
t
t
t
t
10
11
12
13
14
15
16
17
18
19
20
21
22
+ t
1
2
3
4
5
6
7
8
9
BUSY
8
(1)
Bus Access Time and BYTE Delay
Valid Data after DATACLK HIGH
Data Valid Delay after R/C LOW
BUSY Delay after Data Valid
+85 C.
®
Data Valid after DATACLK
External DATACLK Period
External DATACLK HIGH
External DATACLK LOW
after Start of Conversion
Data Valid to DATACLK
CS and R/C to External
DATACLK Setup Time
R/C to CS Setup Time
Convert Pulse Width
Bus Relinquish Time
Previous Data Valid
ADS7807
t
Start of Conversion
Start of Conversion
to DATACLK Delay
End of Conversion
15
t
BUSY Delay from
BUSY Delay after
DATACLK Period
Throughput Time
Conversion Time
13
Acquisition Time
DESCRIPTION
Aperture Delay
HIGH Delay
BUSY LOW
LOW Delay
MSB Valid
1
t
14
(Results from previous conversion.)
Bit 14 Valid
t
16
2
MIN TYP MAX UNITS
0.04
400
100
10
20
12
20
40
50
25
10
25
Bit 13 Valid
600
1.4
1.1
19
19
90
40
19
60
19
75
3
A
= –40 C to
12
20
85
20
20
83
83
25
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
10
t
7
Bit 1 Valid
+ t
8
15
INTERNAL DATA CLOCK (During a Conversion)
To use the internal data clock, tie EXT/INT (pin 8) LOW.
The combination of R/C (pin 22) and CS (pin 23) LOW will
initiate conversion ‘n’ and activate the internal data clock
(typically 900kHz clock rate). The ADS7807 will output 16
bits of valid data, MSB first, from conversion ‘n-1’ on
SDATA (pin 19), synchronized to 16 clock pulses output on
DATACLK (pin 18). The data will be valid on both the
rising and falling edges of the internal data clock. The rising
edge of BUSY (pin 24) can be used to latch the data. After
the 16th clock pulse, DATACLK will remain LOW until the
next conversion is initiated, while SDATA will go to what-
ever logic level was input on TAG (pin 20) during the first
clock pulse. Refer to Table VI and Figure 4.
EXTERNAL DATA CLOCK
To use an external data clock, tie EXT/INT (pin 8) HIGH. The
external data clock is not a conversion clock; it can only be
used as a data clock. To enable the output mode of the
ADS7807, CS (pin 23) must be LOW and R/C (pin 22) must
be HIGH. DATACLK must be HIGH for 20% to 70% of the
total data clock period; the clock rate can be between DC and
10MHz. Serial data from conversion ‘n’ can be output on
SDATA (pin 19) after conversion ‘n’ is completed or during
conversion ‘n + 1’.
An obvious way to simplify control of the converter is to tie
CS LOW and use R/C to initiate conversions.
While this is perfectly acceptable, there is a possible prob-
lem when using an external data clock. At an indeterminate
point from 12 s after the start of conversion ‘n’ until BUSY
rises, the internal logic will shift the results of conversion ‘n’
into the output register. If CS is LOW, R/C HIGH, and the
external clock is HIGH at this point, data will be lost. So,
with CS LOW, either R/C and/or DATACLK must be LOW
during this period to avoid losing valid data.
LSB Valid
16
MSB Valid
1
Bit 14 Valid
2