CS61584A Cirrus Logic, Inc., CS61584A Datasheet - Page 44

• Manufacturer Part Number: CS61584A
• Description: Dual T1/e1 Line Interface
• Manufacturer: Cirrus Logic, Inc.

44
INT - Receive Alarm Interrupt [Host mode] (PLCC pin 7; TQFP pin 63)
IPOL - Interrupt Polarity [Host mode, BTS = 0] (PLCC pin 44; TQFP pin 33)
DTACK - Data Acknowledge [Host mode - parallel port, BTS = 1] (PLCC pin 44; TQFP pin 33)
P/S - Parallel/Serial Port Selection [Host modes] (PLCC pin 25; TQFP pin 16)
RD(DS) - Read Input (Data Strobe) [Host mode - parallel port] (PLCC pin 6; TQFP pin 62)
SAD4, SAD5 - Set Chip Address [Host mode - parallel port]
SAD6, SAD7 - (PLCC pins 24, 45, 16, 53; TQFP pins 15, 34, 7, 42)
SCLK - Serial Clock [Host mode - serial port] (PLCC pin 6; TQFP pin 62)
SDI - Serial Data Input [Host mode - serial port] (PLCC pin 4; TQFP pin 60)
SDO - Serial Data Output [Host mode - serial port] (PLCC pin 5; TQFP pin 61)
SPOL - SDO Polarity Control [Host mode - serial port] (PLCC pin 3; TQFP pin 59)
WR(R/W) - Write Input (Read/Write) [Host mode - parallel port] (PLCC pin 61; TQFP pin 49)
44
An interrupt is generated to flag the host processor when a Status register changes state. The interrupt
is cleared by reading the Status register. The logic level for an active interrupt alarm is controlled by the
IPOL pin. The INT pin is an open drain output and must be tied to the appropriate supply through a
resistor.
When BTS is low (Intel bus timing), the active polarity of the INT pin is controlled by IPOL. An active
high interrupt is generated when IPOL is high. An active low interrupt is generated when IPOL is low.
When the BTS pin is high, this pin becomes DTACK and INT is active low.
When the BTS pin is high (Motorola bus timing), a low pulse on DTACK indicates when the CS61584A
has latched the data during a microprocessor write cycle or when the CS61584A has output data to the
bus during a microprocessor read cycle. The polarity of the INT pin is fixed to active low when the BTS
pin is high (Motorola bus timing).
Selects the method of communication to the internal register set during Host mode operation. Serial port
communication over the SDI, SDO, and SCK pins is selected when P/S is low. Parallel port
communication over an 8-bit, multiplexed address/data bus is selected when P/S is high.
When the BTS pin is low (Intel bus timing), a low pulse on RD selects a read operation when the CS
pin is low. When the BTS pin is high (Motorola bus timing), a high pulse on DS performs a read/write
operation when the CS pin is low.
These pins are hard-wired to establish one of 16 possible device addresses to permit a shared parallel
bus system architecture. The value is compared with the upper nibble of the address byte AD[7:4] as
part of the address decode procedure.
Serial clock used to access the register set. A high or low level can be present on SCLK when the
device is selected using the CS pin.
Serial data input to the register set. Sampled by the device on the rising edge of SCLK.
Serial data output from the register set. If SPOL is low, SDO is valid on the rising edge of SCLK. If
SPOL is high, SDO is valid on the falling edge of SCLK. The SDO pin goes to a high-impedance state
while the serial port is being written or after bit D7 is output on SDO during a read.
Controls the polarity of the serial data output SDO. If SPOL is low, SDO is valid on the rising edge of
SCLK. If SPOL is high, SDO is valid on the falling edge of SCLK.
When the BTS pin is low (Intel bus timing), a low pulse on WR selects a write operation when the CS
pin is low. When the BTS pin is high (Motorola bus timing), a high pulse on R/W selects a read
operation and a low pulse on R/W selects a write operation when the CS pin is low.
DS261PP5
CS61584A
CS61584A
DS261PP5
DS261F1