CS61584A Cirrus Logic, Inc., CS61584A Datasheet - Page 41

• Manufacturer Part Number: CS61584A
• Description: Dual T1/e1 Line Interface
• Manufacturer: Cirrus Logic, Inc.

T1/E1 Data Inputs and Outputs
RCLK1, RCLK2 - Receive Clock (PLCC pins 10, 59; TQFP pins 1, 48)
RPOS1, RPOS2 - Receive Positive Data (PLCC pins 11, 58; TQFP pins 2, 47)
RNEG1, RNEG2 - Receive Negative Data (PLCC pins 12, 57; TQFP pins 3, 46)
RDATA1, RDATA2 - Receive Data [Host mode] (PLCC pins 11, 58; TQFP pins 2, 47)
RTIP1, RTIP2 - Receive Tip (PLCC pins 27, 42; TQFP pins 17, 32)
RRING1, RRING2 - Receive Ring (PLCC pins 28, 41; TQFP pins 18, 31)
TCLK1, TCLK2 - Transmit Clock (PLCC pins 13, 56; TQFP pins 4, 45)
TPOS1, TPOS2 - Transmit Positive Data (PLCC pins 14, 55; TQFP pins 5, 44)
TNEG1, TNEG2 - Transmit Negative Data (PLCC pins 15, 54; TQFP pins 6, 43)
TDATA1, TDATA2 - Transmit Data [Host mode] (PLCC pins 14, 55; TQFP pins 5, 44)
TTIP1, TTIP2 - Transmit Tip (PLCC pins 20,49; TQFP pins 11, 38)
TRING1, TRING2 - Transmit Ring (PLCC pins 23, 46; TQFP pins 14, 35)
Oscillator
1XCLK - One-times Clock Frequency Select (PLCC pin 38; TQFP pin 28)
DS261PP5
DS261F1
The receiver recovered clock and NRZ digital data from RTIP and RRING is output on these pins.
During Hardware mode operation, the CLKE pin determines the clock edge on which RPOS and RNEG
are stable and valid. During Host mode operation, the CLKE bit in the Control A register determines the
clock edge on which RPOS and RNEG are stable and valid. A positive pulse (with respect to ground)
received on RTIP generates a logic 1 on RPOS, and a positive pulse received on RRING generates a
logic 1 on RNEG.
During Host mode operation with the coders enabled, the decoded digital data stream from RTIP and
RRING is output on RDATA in NRZ format. The CLKE bit in the Control A register determines the clock
edge on which RDATA is stable and valid.
The receive AMI signal from the line interface is input on these pins. The recovered clock and data are
output on RCLK, RPOS, and RNEG (or RDATA).
The transmit clock and data are input to these pins. The signal is driven to the line interface at TTIP
and TRING. Data on TPOS and TNEG are sampled on the falling edge of TCLK. An input on TPOS
causes a positive pulse to be transmitted at TTIP and TRING, while an input on TNEG causes a
negative pulse to be transmitted at TTIP and TRING.
During Host mode operation with the coders enabled, the un-encoded digital data stream is input on
TDATA in NRZ format. Data at TDATA is sampled on the falling edge of TCLK.
The transmit AMI signal to the line interface is output on these pins. The transmit clock and data are
input on TCLK, TPOS, and TNEG (or TDATA).
When 1XCLK is high, REFCLK must be a 1X clock (i.e., 1.544 MHz for T1 applications or 2.048 MHz
for E1 applications). When 1XCLK is low, REFCLK must be an 8X clock (i.e., 12.352 MHz for T1
applications or 16.384 MHz for E1 applications).
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