MAX791 Maxim, MAX791 Datasheet - Page 10

• Manufacturer Part Number: MAX791
• Description: Microprocessor Supervisory Circuit
• Manufacturer: Maxim

dog-timeout period, WDO goes low 70ns after the
falling edge of WDPO and remains low until the next
transition at WDI (Figure 5). A flip-flop can force the
system into a hardware shutdown if there are two suc-
cessive watchdog faults (Figure 6). WDO has a 2 x TTL
output characteristic.
As described in the preceding section, WDPO can be
used as the clock input to an external D flip-flop. Upon
the absence of a watchdog edge or pulse at WDI at the
end of a watchdog-timeout period, WDPO will pulse low
for 1ms. The falling edge of WDPO precedes WDO by
70ns. Since WDO is high when WDPO goes low, the
flip-flop’s Q output remains high as WDO goes low
(Figure 5). If the watchdog timer is not reset by a transi-
tion at WDI, WDO remains low and WDPO clocks a
logic low to the Q output, causing the MAX791 to latch
in reset. If the watchdog timer is reset by a transition at
WDI, WDO goes high and the flip-flop’s Q output
remains high. Thus, a system shutdown is only caused
by two successive watchdog faults.
The internal pull-up resistors associated with WDO and
WDPO connect to V
these outputs directly to CMOS logic that is powered
from V
Microprocessor Supervisory Circuit
Figure 6. Two consecutive watchdog faults latch the system in reset.
10
______________________________________________________________________________________
CC
since, in the absence of V
REACTIVATE
*SETS Q HIGH ON POWER-UP
+5V
+5V
OUT
Watchdog-Pulse Output
. Therefore, do not connect
*1 F
3.6V
CC
4.7k
(i.e., battery
1
9
VBATT
MR
MAX791
GND
V
4
LOWLINE
CC
3
RESET
WDPO
V
WDO
WDI
OUT
2
15
11
16
14
10
mode), excessive current will flow from WDO or
WDPO through the protection diode(s) of the CMOS-
logic inputs to ground.
SWT input controls the watchdog-timeout period.
Connecting SWT to V
watchdog-timeout period. Select an alternative timeout
period by connecting a capacitor between SWT and
GND. Do not leave SWT floating, and do not connect it
to ground. The following formula determines the watch-
dog-timeout period:
This formula is valid for capacitance values between
4.7nF and 100nF (see the Watchdog Timeout vs.
Timing Capacitor graph in the Typical Operating
Characteristics ). SWT is internally connected to a
±100nA (typ) current source, which charges and dis-
charges the timing capacitor to create the oscillator fre-
quency that sets the watchdog timeout period (see
Connecting a Timing Capacitor to SWT in the
Applications Information section).
1/6 74HC04
5
D
0.1 F
Watchdog Timeout Period = 2.1 x (capacitor value
in nF) ms
CLOCK
SET
3
6
CD4013
RESET V
V
CC
Selecting an Alternative Watchdog
4
14
SS
7
Q
Q
1
2
OUT
selects the internal 1.6sec
RESET
I/O
NMI
INTERRUPT
P POWER
CONSECUTIVE
INDICATIONS
WATCHDOG
FAULT
P
TWO
Timeout Period