MCIMX31 Motorola Semiconductor Products, MCIMX31 Datasheet - Page 62

no-image

MCIMX31

Manufacturer Part Number
MCIMX31
Description
Manufacturer
Motorola Semiconductor Products
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX31CJKN5D
Manufacturer:
AVAGO
Quantity:
1 001
Part Number:
MCIMX31CJKN5D
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX31CJMN4C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX31CJMN4CR2
Manufacturer:
SPANSION
Quantity:
2 500
Part Number:
MCIMX31CJMN4CR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX31CJMN4D
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX31CJMN4DR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX31CVKN5C
Manufacturer:
FREESCALE
Quantity:
201
Part Number:
MCIMX31CVKN5D
Manufacturer:
NXP
Quantity:
210
Part Number:
MCIMX31CVKN5D
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MCIMX31CVMN4D
Manufacturer:
AD
Quantity:
200
Part Number:
MCIMX31CVMN4D
Manufacturer:
FREESCALE
Quantity:
20 000
3
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
Electrical Characteristics
4.3.15.3 Interface to Sharp HR-TFT Panels
Figure 49
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics,” on page 59.
The timing images correspond to straight polarity of the Sharp signals.
62
Tdicu
Display interface clock up time
DISPB_D3_DATA
DISPB_D3_SPL
DISPB_D3_CLS
DISPB_D3_REV
=
DISPB_D3_PS
DISPB_D3_CLK
DISPB_D3_HSYNC
1
-- - T
2
depicts the Sharp HR-TFT panel interface timing, and
HSP_CLK ceil
Figure 49. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level
2 DISP3_IF_CLK_UP_WR
--------------------------------------------------------------------- -
HSP_CLK_PERIOD
SPL pulse width is fixed and aligned to the first data of the line.
Example is drawn with FW+1=320 pixel/line, FH+1=240 lines.
REV toggles every HSYNC period.
MCIMX31/MCIMX31L Advance Information, Rev. 3.2
IP24
IP22
Preliminary—Subject to Change Without Notice
Horizontal timing
IP21
IP23
IP25
D1 D2
IP26
1 DISPB_D3_CLK period
Table 49
D320
lists the timing parameters. The
Freescale Semiconductor

Related parts for MCIMX31