LPC2101 Philips Semiconductors (Acquired by NXP), LPC2101 Datasheet - Page 19

• Manufacturer Part Number: LPC2101
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
LPC2101_02_03_1
Preliminary data sheet
6.17.7 Power control
6.17.8 APB bus
6.18.1 EmbeddedICE
6.18 Emulation and debugging
The LPC2101/2102/2103 supports two reduced power modes: Idle mode and
Power-down mode.
In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.
Peripheral functions continue operation during Idle mode and may generate interrupts to
cause the processor to resume execution. Idle mode eliminates power used by the
processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip output pins remain
static. The Power-down mode can be terminated and normal operation resumed by either
a reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip
RTC will enable the microcontroller to have the RTC active during Power-down mode.
Power-down current is increased with RTC active. However, it is significantly lower than in
Idle mode.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings during active
and Idle mode.
The APB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via APB bus so that they can operate at
the speed chosen for the ARM processor. In order to achieve this, the APB bus may be
slowed down to
properly at power-up (and its timing cannot be altered if it does not work since the APB
divider control registers reside on the APB bus), the default condition at reset is for the
APB bus to run at
is to allow power savings when an application does not require any peripherals to run at
the full processor rate. Because the APB divider is connected to the PLL output, the PLL
remains active (if it was running) during Idle mode.
The LPC2101/2102/2103 support emulation and debugging via a JTAG serial port.
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote
Debug Protocol commands to the JTAG data needed to access the ARM core.
The ARM core has a Debug Communication Channel function built-in. The debug
communication channel allows a program running on the target to communicate with the
host debugger or another separate host without stopping the program flow or even
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2
1
to
4
of the processor clock rate. The second purpose of the APB divider
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Rev. 01 — 18 January 2006
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of the processor clock rate. Because the APB bus must work
Single-chip 16-bit/32-bit microcontrollers
LPC2101/2102/2103
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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