LPC2131 Philips Semiconductors (Acquired by NXP), LPC2131 Datasheet - Page 23

• Manufacturer Part Number: LPC2131
• Manufacturer: Philips Semiconductors (Acquired by NXP)

Philips Semiconductors
9397 750 14008
Preliminary data sheet
6.21.4 Brown-out detector
6.21.5 Code security
6.21.6 External interrupt inputs
6.21.7 Memory Mapping Control
6.21.8 Power Control
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
The LPC2131/2132/2138 include 2-stage monitoring of the voltage on the V
voltage falls below 2.9 V, the BOD asserts an interrupt signal to the Vectored Interrupt
Controller. This signal can be enabled for interrupt; if not, software can monitor the signal
by reading dedicated register.
The second stage of low-voltage detection asserts reset to inactivate the
LPC2131/2132/2138 when the voltage on the V
prevents alteration of the Flash as operation of the various elements of the chip would
otherwise become unreliable due to low voltage. The BOD circuit maintains this reset
down below 1 V, at which point the POR circuitry maintains the overall reset.
Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
This feature of the LPC2131/2132/2138 allow an application to control whether it can be
debugged or protected from observation.
If after reset on-chip boot-loader detects a valid checksum in Flash and reads
0x87654321 from address 0x1FC in Flash, debugging will be disabled and thus the code
in Flash will be protected from observation. Once debugging is disabled, it can be enabled
only by performing a full chip erase.
The LPC2131/2132/2138 include up to nine edge or level sensitive External Interrupt
Inputs as selectable pin functions. When the pins are combined, external events can be
processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake up the processor from Power-down mode.
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x00000000. Vectors may be mapped to the bottom of the on-chip
Flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
The LPC2131/2132/2138 support two reduced power modes: Idle mode and Power-down
mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates power used
by the processor itself, memory systems and related controllers, and internal buses.
Rev. 01 — 18 November 2004
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ramp (in the case of power on), the type of crystal
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LPC2131/2132/2138
Single-chip 16/32-bit microcontrollers
pins falls below 2.6 V. This reset
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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pins. If this
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