AT94K ATMEL Corporation, AT94K Datasheet - Page 23

• Manufacturer Part Number: AT94K
• Description: 5K - 40K Gates of At40k FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE
• Manufacturer: ATMEL Corporation

Rev. 1138F–FPSLI–06/02
Figure 19. FPSLIC Configurable Allocation SRAM Memory
Notes:
$0FFF
$3FFF
$2FFF
$1FFF
$1000
$005F
$0000
$3000
$2000
$001F
1. The Soft “BOOT BLOCK” is an area of memory that is first loaded when the part is powered
2. The lower portion of the Data memory is not shared between the AVR and FPGA. The AVR
up and configured. The remainder of the memory can be reprogrammed while the device is
in operation for switching functions in and out of memory. The Soft “BOOT BLOCK” can only
be programmed by a full device configuration on power-up.
uses addresses $0000 - $001F for the AVR CPU general working registers. $001F - $005F
are the addresses used for Memory Mapped I/O and store the information in dedicated reg-
isters. Therefore, on the FPGA side $0000 - $005F are available for data that is only needed
by the FPGA.
ACCESS
SRAM
FPGA
DATA
ONLY
Data SRAM Memory
4 Kbytes x 8
4 Kbytes x 8
4 Kbytes x 8
4 Kbytes x 8
OPTIONAL
OPTIONAL
OPTIONAL
FIXED
AVR REG.
MEMORY
MAPPED
during Development
SPACE
AVR
I/O
Memory Partition
is User Defined
(2)
AT94K Series FPSLIC
Program SRAM Memory
SOFT “BOOT BLOCK”
4 Kbytes x 16 (94K05)
(1)(2)
2 Kbytes x 16
2 Kbytes x 16
2 Kbytes x 16
OPTIONAL
OPTIONAL
OPTIONAL
10K x 16
FIXED
(1)
$2FFF
$3000
$3FFF
$0000
$07FF
$27FF
$2800
$37FF
$3800
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