AT94K ATMEL Corporation, AT94K Datasheet - Page 121

• Manufacturer Part Number: AT94K
• Description: 5K - 40K Gates of At40k FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE
• Manufacturer: ATMEL Corporation

Data Reception
Rev. 1138F–FPSLI–06/02
Figure 65 shows a block diagram of the UART Receiver.
Figure 65. UART Receiver
Note:
The receiver front-end logic samples the signal on the RXDn pin at a frequency 16 times the
baud-rate. While the line is idle, one single sample of logic 0 will be interpreted as the falling
edge of a start bit, and the start bit detection sequence is initiated. Let sample 1 denote the
first zero-sample. Following the 1-to-0 transition, the receiver samples the RXDn pin at sam-
ples 8, 9 and 10. If two or more of these three samples are found to be logic 1s, the start bit is
rejected as a noise spike and the receiver starts looking for the next 1-to-0 transition.
XTAL
PE1/
PE3
1. n = 0, 1
PIN CONTROL
GENERATOR
BAUD RATE
LOGIC
RXDn
(1)
BAUD x 16
DATA RECOVERY
LOGIC
UART CONTROL AND
STATUS REGISTER
DATA BUS
/16
(UCSRnB)
STORE UDRn
BAUD
AT94K Series FPSLIC
DATA BUS
RXCn
IRQ
UART CONTROL AND
STATUS REGISTER
SHIFT REGISTER
REGISTER (UDRn)
(UCSRnA)
10(11)-BIT RX
UART I/O DATA
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