AT91M55800A ATMEL Corporation, AT91M55800A Datasheet - Page 2

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AT91M55800A

Manufacturer Part Number
AT91M55800A
Description
The AT91M55800A Features 8K Bytes of On-chip SRAM, an External Bus Interface, a 6-channel Timer/Counter, 3 Usarts, a Master/slave Spi Interface, a Watchdog Timer, an 8-channel 10-bit ADC, a 2-channel 10-bit DAC, a Clock Generator, Real-time Clock And
Manufacturer
ATMEL Corporation
Datasheet

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Figure 1. NWAIT Rising
Figure 2. Number of Standard Wait States is Two
Note:
2
MCKI
NWAIT
NCS
The following waveforms further explain the issue:
If the NWAIT setup time is satisfied on the first rising edge of MCKI, the behavior is accurate. The EBI operations are
not affected when the NWAIT rises.
If the NWAIT setup time is satisfied on the following edges of MCKI and if at least one standard wait state remains to be
executed, the behavior is accurate. In the following example, the number of standard wait states is two. The NWAIT
setup time on the second rising edge of MCKI must be met.
1. These numbers refer to the standard access cycles.
NWAIT
AT91M55800A Errata Sheet
MCKI
1
(1)
Standard Access Length with Two Wait States
NWAIT Setup before MCKI Rising (EB16)
EB16
2
(1)
3
(1)
1780B–01/02

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