ADA4841-1YRZ Analog Devices, ADA4841-1YRZ Datasheet - Page 6

• Manufacturer Part Number: ADA4841-1YRZ
• Manufacturer: Analog Devices

ADA4841-1
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature
Junction Temperature
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
specified for device soldered in circuit board for surface-mount
packages.
Table 5. Thermal Resistance
Package Type
8-lead SOIC
Maximum Power Dissipation
The maximum safe power dissipation for the ADA4841-1 is
limited by the associated rise in junction temperature (T
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit may change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the amplifiers. Exceeding a
junction temperature of 150°C for an extended period can
result in changes in silicon devices, potentially causing
degradation or loss of functionality.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
JA
is specified for the worst-case conditions, that is, θ
Rating
12.6 V
See Figure 3
−V
±1.8 V
−65°C to +125°C
−40°C to +85°C
JEDEC J-STD-20
150°C
θ
125
JA
S
− 0.5 V to +V
Unit
°C/W
S
JA
+ 0.5 V
is
J
) on
Rev. A | Page 6 of 20
The power dissipated in the package (P
quiescent power dissipation and the power dissipated in the die
due to the amplifier’s drive at the output. The quiescent power is
the voltage between the supply pins (V
current (I
RMS output voltages should be considered. If R
to −V
V
worst case, when V
In single-supply operation with R
is V
Airflow increases heat dissipation, effectively reducing θ
In addition, more metal directly in contact with the package
leads and through holes under the device reduces θ
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(125°C/W) on a JEDEC standard 4-layer board. θ
approximations.
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
S
× I
OUT
P
P
P
S
OUT
D
D
D
, as in single-supply operation, the total drive power is
2.0
1.5
1.0
0.5
= V
= Quiescent Power + (Total Drive Power − Load Power)
=
=
0
. If the rms signal levels are indeterminate, consider the
S
).
(
(
V
V
S
–55
/2.
S
S
×
×
I
I
–35
S
S
)
)
+
+
OUT
⎛
⎜
⎝
(
–15
V
V
AMBIENT TEMPERATURE (°C)
2
= V
S
R
S
4 /
L
×
)
S
V
2
5
/4 for R
R
OUT
SOIC
L
25
⎞
⎟
⎠
L
–
L
referenced to −V
V
to midsupply.
45
OUT
R
S
L
D
) times the quiescent
) is the sum of the
2
65
85
L
is referenced
JA
JA
values are
105
S
, worst case
.
JA
125
.