ADA4841-1YRZ Analog Devices, ADA4841-1YRZ Datasheet - Page 15

• Manufacturer Part Number: ADA4841-1YRZ
• Manufacturer: Analog Devices

Figure 43 shows the amplifier’s frequency response as a G = −1
inverter with the input and output stage biased near the
negative supply rail.
The input voltage (V
0 V, see Figure 37. +V
−200 mV to −20 mV. With the input and output voltages biased
200 mV from the bottom rail, the G = −1 inverter frequency
response is not much different from what is seen with the input
and output voltages biased near midsupply. At 150 mV bias, the
frequency response starts to decrease and at 20 mV, the inverter
band-width is less than half its nominal value.
CAPACITANCE DRIVE
Capacitance at the output of an amplifier creates a delay within
the feedback path that, if within the bandwidth of the loop, can
create excessive ringing and oscillation. The G = +1 follower
topology has the highest loop bandwidth of any typical
configuration and therefore is the most vulnerable to the
effects of capacitance load.
A small resistor in series with the amplifier’s output and the
capacitive load mitigates the problem. Figure 44 plots the
recommended series resistance vs. the capacitance for gains
of +1, +2, and +5.
Figure 43. Small Signal Frequency Response vs. Negative Supply Bias
–12
–3
–6
–9
6
3
0
0.1
V
G = –1
V
S+
IN
= 20mV p-p
= 5V
V
IN
S–
S
) and reference voltage (V
is biased at +5 V, and −V
= –50mV
1
FREQUENCY (MHz)
V
V
S–
S–
= –20mV
= –100mV
10
V
S–
= –150mV
S
V
IP
S–
is swept from
) are both at
= –200mV
100
Rev. A | Page 15 of 20
INPUT PROTECTION
The ADA4841-1 is fully protected from ESD events,
withstanding ESD events of 2.5 keV with no measured
performance degradation. The precision input is protected
with an ESD network between the power supplies and diode
clamps across the input device pair, as shown in Figure 45.
For differential voltages above approximately 1.4 V, the diode
clamps start to conduct. Too much current can cause damage
due to excessive heating. If large differential voltages need to be
sustained across the input terminals, it is recommended that the
current through the input clamps be limited to below 150 mA.
Series input resistors sized appropriately for the expected
differential overvoltage provide the needed protection.
The ESD clamps start to conduct for input voltages more than
0.7 V above the positive supply and input voltages more than
0.7 V below the negative supply. It is recommended that the
fault current be limited to less than 150 mA if an overvoltage
condition is expected.
60
50
40
30
20
10
0
10
Figure 44. Series Resistance vs. Capacitive Load
VCC
VEE
Figure 45. Input Stage and Protection Diodes
VP
ESD
ESD
TO REST OF AMPLIFIER
G = +2
BIAS
CAPACITANCE LOAD (pF)
100
G = +1
G = +5
1000
ESD
ESD
VN
ADA4841-1
10000