MAX5130 Maxim Integrated Products, MAX5130 Datasheet - Page 13

• Manufacturer Part Number: MAX5130
• Description: (MAX5130 / MAX5131) Voltage-output DACs
• Manufacturer: Maxim Integrated Products

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Table 3. Detailed SSPCON Register Contents
X = Don’t care
Table 4. Detailed SSPSTAT Register Contents
X = Don’t care
The contents of the internal shift register are output
serially on DOUT, allowing for daisy-chaining (see
Applications Information ) of multiple devices as well as
data readback. The MAX5130/MAX5131 may be pro-
grammed to shift data out on DOUT on the serial
clock’s rising edge (Mode 1) or falling edge (Mode 0).
The latter is the default during power-up and provides a
lag of 16 clock cycles, maintaining SPI, QSPI,
MICROWIRE, and PIC16/PIC17 compatibility. In Mode
1, the output data lags DIN by 15.5 clock cycles.
During power-down, DOUT retains its last digital state
prior to shutdown.
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
WCOL
CKP
SMP
CKE
R/W
D/A
UA
BF
P
S
CONTROL BIT
CONTROL BIT
+3V/+5V, 13-Bit, Serial Voltage-Output DACs
______________________________________________________________________________________
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
Serial Data Output
MAX5130/MAX5131
MAX5130/MAX5131
SETTINGS
SETTING
X
X
1
0
0
0
0
1
0
1
X
X
X
X
X
X
Write Collision Detection Bit
Receive Overflow Detection Bit
Synchronous Serial Port Enable Bit
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI as
Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.
Synchronous Serial Port Mode Select Bit. Sets SPI master mode
and selects f
SPI Data Input Sample Phase. Input data is sampled at the mid-
dle of the data output time.
SPI Clock Edge Select Bit. Data will be transmitted on the rising
edge of the serial clock.
Data Address Bit
Stop Bit
Start Bit
Read/Write Bit Information
Update Address
Buffer Full Status Bit
with Internal Reference
serial-port pins.
The UPO feature allows an external device to be con-
trolled through the serial-interface setup (Table 1),
thereby reducing the number of microcontroller I/O
ports required. During power-down, this output will
retain the last digital state before shutdown. With CLR
pulled low, UPO will reset to the default state after
wake-up.
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
CLK
User-Programmable Output (UPO)
= f
OSC
/ 16.
(SSPSTAT)
(SSPCON)
13