WM8711 Wolfson Microelectronics Ltd., WM8711 Datasheet - Page 17

• Manufacturer Part Number: WM8711
• Description: Internet Audio DAC With Integrated Headphone Driver
• Manufacturer: Wolfson Microelectronics Ltd.

WM8711
Figure 13 Left Justified Mode
WOLFSON MICROELECTRONICS LTD
DACLRC
DACDAT
BCLK
MSB
1
2
CLKOUT can also be divided by 2 under software control, refer to Table 7. Note that if CLKOUT is
not required then the CLKOUT buffer on the WM8711 can be safely powered down to conserve
power (see POWER DOWN section). If the system architect has the choice between using F
F
divide by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical
Characteristics for timing information.
Table 7 Programming CLKOUT
CLKOUT is disabled and set low whenever the device is in reset.
DIGITAL AUDIO INTERFACES
WM8711 may be operated in either one of the 4 offered audio interface modes. These are:
All four of these modes are MSB first and operate with data 16 to 32 bits, except in right justified
mode where 32 bit data is not supported.
The digital audio interface receives the digital audio data for the internal DAC digital filters on the
DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters
with left and right channels multiplexed together. DACLRC is an alignment clock that controls
whether Left or Right channel data is present on DATDAT. DACDAT and DACLRC are synchronous
with the BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always
an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in master
or slave mode. Refer to the MASTER/SLAVE OPERATION section
There are four digital audio interface formats accommodated by the WM8711. These are shown in
the figures below. Refer to the Electrical Characteristic section for timing information.
Left Justified mode is where the MSB is available on the first rising edge of BCLK following a
DACLRC transition.
I2S mode is where the MSB is available on the 2nd rising edge of BCLK following a LRCLK
transition.
3
MCLK
0001000
Sampling
Control
REGISTER
ADDRESS
Right justified
Left justified
I2S
DSP mode
or F
LEFT CHANNEL
CLKOUT
n-2 n-1
= F
7
BIT
MCLK
/2 in the interface, the latter is recommended to conserve power. When the
n
LSB
CLKODIV2
LABEL
MSB
1/fs
1
0
DEFAULT
2
3
RIGHT CHANNEL
CLKOUT divider select
1 = CLOCKOUT is Core Clock
divides by 2
0 = CLOCKOUT is Core Clock
n-2 n-1
DESCRIPTION
PP Rev 1.2 November 2000
n
LSB
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CLKOUT
17
=