WM8146 Wolfson Microelectronics Ltd., WM8146 Datasheet - Page 8

• Manufacturer Part Number: WM8146
• Description: 12-bit ( 8+4-bit ) Linear Sensor Image Processor
• Manufacturer: Wolfson Microelectronics Ltd.

WM8146
CDS/NON-CDS PROCESSING
WOLFSON MICROELECTRONICS LTD
TIMING
Figure 6 illustrates the use of the RLC pin, MCLK and VSMP to control the timing of the CL pulse for
a typical CCD waveform. The CL pulse is applied during the reset period.
The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during
each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal
CL pulse on the next reset level. The position of CL can be adjusted by using control bits
CDSREF[1:0], as shown in Figure 7.
The VRLC pin outputs the analogue RLC voltage selected via control set-up register 3 bits RLC[1:0].
Figure 6 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this controls switch 2 (Figure 5) and causes the signal reference to come from
the video reset level. The time at which the reset level is sampled, by clock R
programming control bits CDSREF[1:0], as shown in Figure 7 .
For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed
with respect to the reference voltage VMID.
Figure 7 Reset Sample and Clamp Timing
(CDSREF = 01)
INPUT VIDEO
R
R
R
R
S
S
S
S
/CL (CDSREF = 00)
/CL (CDSREF = 01)
/CL (CDSREF = 10)
/CL (CDSREF = 11)
MCLK
VSMP
RLC
CL
R G B
1
MCLK
V S M P
Programmable Delay
VS
X
X
RLC on this Pixel
R G B
0
X
X
No RLC on this Pixel
PP Rev 1.1 January 2000
s
/CL, is adjustable by
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R G B
0
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