WM8143-12 Wolfson Microelectronics Ltd., WM8143-12 Datasheet - Page 10

• Manufacturer Part Number: WM8143-12
• Description: WM8143 : 10 or 12-BIT, 4MSPS Analogue Front End For CCD Image Sensors
• Manufacturer: Wolfson Microelectronics Ltd.

WM8143-12
For the input stage, the final analogue voltage applied
to the ADC can be expressed as:
Where V
G is the programmed gain
V
V
DSIGN is the Offset DAC sign bit
DAC_CODE is the offset DAC value.
V
The ADC has a lower reference of V
and an upper reference of V
an ADC input voltage is applied to the ADC equal to
V
voltage is applied to the ADC equal to V
code is FFF(hex).
Reset Level Clamp
Both CDS and Single Ended operation can be used
with
configuration is shown in Figure 4.
Figure 4 Typical Input Configuration Using Reset
Level Clamping
The position of the clamp relative to the video sample
is
programmable by CDSREF1-0 (see Table 6).
default, the reset sample occurs on the fourth MCLK
rising edge after VSMP. The relative timing between
the reset sample (and CL) and video sample can be
altered as shown in Figure 5. When the clamp pulse is
active the voltage on the WM8143-12 side of Cin, i.e.
RINP, will be forced to be equal to the VRLC clamp
voltage. The VRLC clamp voltage is programmable to
three different levels via the serial interface.
voltage to which the clamp voltage should be
programmed is dependent on the type of sampling
selected and the polarity of the input video signal.
V
ADC
VS
RS
MID
RB
is the voltage of the video sample.
is the voltage of the reset sample,
shown
the resulting code is 000(hex). When an ADC input
is the WM8143-12 generated V
G
Reset
*
Cin
ADC
(V
VS
is the voltage applied, to the ADC
diagramatically
V
RS
RINP
Level
)
VRLC
[
(1
2
VMID
*
Clamping.
DSIGN)
RS
VS
RT
in
S/H
S/H
*
(typically 3.5 V). When
DAC_CODE
Figure
255
MID
RB
A
WM8143-12
Wolfson Microelectronics
voltage.
(typically 1.5 V)
+
-
RT
typical
Gain=G
*
the resulting
V
6
2
MID
]
and
V
MID
input
The
By
is
10
Figure 5 Reset Sample and Clamp Timing
For CDS operation it is important to match the clamp
voltage to the amplitude and polarity of the video
signal. This will allow the best use of the wide input
common-mode range offered by the WM8143-12. If the
input video is positive going it is advisable to clamp to
VCL (Lower clamp voltage). If the video is negative
going it is advisable to clamp to VCU (Upper clamp
voltage). Regardless of where the video is clamped the
offset DAC is programmed to move the ADC output
corresponding to the reset level to an appropriate value
to maximise the ADC dynamic range. For Single Ended
operation it is recommended that the clamp voltage is
set to VCM (middle clamp voltage).
Figure 6 Position of Clamp Relative to Video Input
A reset level clamp is activated if the RLC pin is high
on an MCLK rising edge (Figure 7). By default this
initiates an internal clamp pulse three MCLK pulses
later (shown as CL in Figure 5). The relationship
between CL and RS is fixed. Therefore altering the RS
position also alters the CL position (Figure 5). Table 6
shows the three possible voltages to which the reset
level can be clamped.
(default)
CLAMP PULSE
VIDEO INPUT
01
11
VSMP
MCLK
RS
RS
RS
RS
VS
CL
CL
CL
CL
PD. Rev 4 Nov. 99
Production Data