MAX3882A Maxim Integrated Products, MAX3882A Datasheet - Page 8

• Manufacturer Part Number: MAX3882A
• Description: 2.488Gbps 1:4 Demultiplexer
• Manufacturer: Maxim Integrated Products

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2.488Gbps 1:4 Demultiplexer with Clock and
Data Recovery and Limiting Amplifier
The SDI inputs of the MAX3882A accept serial NRZ
data at 2.488Gbps with 10mV
tude. The input sensitivity is 10mV
tolerance is met for a BER of 10
adjust is not used. The input sensitivity is as low as
4mV
to directly interface with a transimpedance amplifier
(MAX3277).
For applications when vertical threshold adjustment is
needed, the MAX3882A can be connected to the out-
put of an AGC amplifier (MAX3861). Here, the input
voltage range is 50mV
Procedure section for decision threshold adjust.
The phase detector in the MAX3882A produces a volt-
age proportional to the phase difference between the
incoming data and the internal clock. Because of its
feedback nature, the PLL drives the error voltage to
zero, aligning the recovered clock to the center of the
incoming data eye for retiming.
The digital frequency detector (FD) acquires frequency
lock without using an external reference clock. The fre-
quency difference between the received data and the
VCO clock is derived by sampling the in-phase and
quadrature VCO outputs on both edges of the data
input signal. Depending on the polarity of the frequency
difference, the FD drives the VCO until the frequency
difference is reduced to zero. Once frequency acquisi-
tion is complete, the FD returns to a neutral state. False
locking is eliminated by this digital frequency detector.
The fully integrated PLL has a second-order transfer
function, with a loop bandwidth (f
external capacitor between V
damping of the PLL. All jitter specifications are based
on the C
Table 1. Operation Modes
8
FREFSET
_______________________________________________________________________________________
P-P
X
X
1
0
for a BER of 10
FIL
capacitor being 0.068µF. Note that the PLL
1
1
0
0
P-P
-10
. The MAX3882A is designed
to 600mV
Loop Filter and VCO
CC_
Frequency Detector
P-P
-10
SIS
L
VCO and FIL sets the
P-P
) fixed at 1.7MHz. An
0
1
X
X
to 1600mV
Phase Detector
P-P
when the threshold
Input Amplifier
, at which the jitter
. See the Design
Normal operation: PLL locked to data input at 2.488Gbps
System loopback: PLL lock frequency at 2.488Gbps
Clock holdover: PLL locked to reference frequency at 155MHz
Clock holdover: PLL locked to reference frequency at 622MHz
P-P
ampli-
jitter transfer bandwidth does not change as the exter-
nal capacitor changes, but the jitter peaking, acquisi-
tion time, and loop stability are affected.
For an overdamped system (f
peaking (J
mated by:
The PLL zero frequency (f
capacitor (CFIL) and can be approximated according to:
Figures 6 and 7 show the open-loop and closed-loop
transfer functions. The PLL acquisition time is also
directly proportional to the external capacitor C
The LOL output indicates a PLL lock failure, either due
to excessive jitter present at data input or due to loss of
input data. In the case of loss of input data, the LOL
indicates a loss-of-signal condition. The LOL output is
asserted low when the PLL loses lock.
The MAX3882A’s clock and data outputs are LVDS
compatible to minimize power dissipation, speed tran-
sition time, and improve noise immunity. These outputs
comply with the IEEE LVDS specification. The differen-
tial output signal magnitude is 250mV to 400mV.
The MAX3882A provides a differential output clock
(PCLK). Table 1 shows the pin configuration for choos-
ing the type of operation mode.
Decision threshold adjust is available for WDM applica-
tions where optical amplifiers are used, generating
spontaneous optical noise at data logic high. The deci-
sion threshold adjust range is ±170mV. Use the provid-
ed 2.2V bandgap reference V
source, such as an output from a DAC to control the
OPERATION MODE DESCRIPTION
P
) of a second-order system can be approxi-
Output LVDS Interface: PD, PCLK
J
f
P
Z
= 20log(1 + f
= 1/2π(650)C
Decision Threshold Adjust
Z
) is a function of the external
Design Procedure
Loss-of-Lock Monitor
Z
REF
/f
Z
FIL
/f
L
L
) < 0.25, the jitter
)
pin or an outside
FIL
.