MAX3882A Maxim Integrated Products, MAX3882A Datasheet - Page 7

• Manufacturer Part Number: MAX3882A
• Description: 2.488Gbps 1:4 Demultiplexer
• Manufacturer: Maxim Integrated Products

www.DataSheet4U.com
The MAX3882A deserializer with clock and data recov-
ery and limiting amplifier converts 2.488Gbps serial
data to clean 4-bit-wide, 622Mbps LVDS parallel data.
The device combines a limiting amplifier with a fully inte-
grated phase-locked loop (PLL), data retiming block, 4-
bit demultiplexer, clock divider, and LVDS output buffer
(Figure 5). The PLL consists of a phase/frequency
detector (PFD), loop filter, and voltage- controlled oscil-
lator (VCO). The MAX3882A is designed to deliver the
best combination of jitter performance and power dissi-
Figure 1. Definition of Input Voltage Swing
Figure 3. Definition of Clock-to-Q Delay
(PD+) - (PD-)
V
V
V
V
PCLK+
CC
CC
CC
CC
+ 0.4V
- 0.4V
- 0.4V
- 0.8V
V
V
CC
CC
2.488Gbps 1:4 Demultiplexer with Clock and
t
CK-Q
(b) DC-COUPLED SINGLE-ENDED INPUT
(a) AC-COUPLED SINGLE-ENDED INPUT
_______________________________________________________________________________________
Detailed Description
t
CK
Data Recovery and Limiting Amplifier
800mV
800mV
5mV
5mV
pation by using a fully differential signal architecture
and low-noise design techniques.
The input signal to the device (SDI) passes through a
DC offset control block, which balances the input signal
to a zero crossing at 50%. The PLL recovers the serial
clock from the serial input data stream and produces
the properly aligned data and the buffered recovered
clock. The frequency of the recovered clock is divided
by four and converted to differential LVDS parallel out-
put PCLK. The demultiplexer generates 4-bit-wide
622Mbps parallel data.
Figure 2. Relationship Between Control Voltage and Threshold
Voltage
Figure 4. LOL Assert Time and PLL Acquisition Time
Measurement
INPUT DATA
LOL OUTPUT
+188
+170
+152
-152
-170
-188
V
TH
(mV)
0.3
LOL ASSERT TIME
2.488Gbps PRBS 2
1.1
23
- 1
THRESHOLD-SETTING ACCURACY
(PART-TO-PART VARIATION OVER PROCESS)
THRESHOLD-SETTING STABILITY
(OVER TEMPERATURE AND POWER SUPPLY)
1.3
2.1
2.488Gbps PRBS 2
ACQUISITION TIME
V
CTRL
23
- 1
(V)
7